• Benjamin Herrenschmidt's avatar
    powerpc/mm: Fix lazy icache flush on pre-POWER5 · dd7b2f03
    Benjamin Herrenschmidt authored
    On 64-bit CPUs with no-execute support and non-snooping icache, such as
    970 or POWER4, we have a software mechanism to ensure coherency of the
    cache (using exec faults when needed).
    
    This was broken due to a logic error when the code was rewritten
    from assembly to C, previously the assembly code did:
    
      BEGIN_FTR_SECTION
             mr      r4,r30
             mr      r5,r7
             bl      hash_page_do_lazy_icache
      END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
    
    Which tests that:
       (cpu_features & (NOEXECUTE | COHERENT_ICACHE)) == NOEXECUTE
    
    Which says that the current cpu does have NOEXECUTE, but does not have
    COHERENT_ICACHE.
    
    Fixes: 91f1da99 ("powerpc/mm: Convert 4k hash insert to C")
    Fixes: 89ff7250 ("powerpc/mm: Convert __hash_page_64K to C")
    Fixes: a43c0eb8 ("powerpc/mm: Convert 4k insert from asm to C")
    Cc: stable@vger.kernel.org # v4.5+
    Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
    Reviewed-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
    [mpe: Change log verbosification]
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    dd7b2f03
hash64_4k.c 3.7 KB