• James Hogan's avatar
    clk-divider: Fix READ_ONLY when divider > 1 · e6d5e7d9
    James Hogan authored
    Commit 79c6ab50 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in
    v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the
    recalc_rate() and round_rate() clock callbacks to be omitted.
    
    However using this flag has the unfortunate side effect of causing the
    clock recalculation code when a clock rate change is attempted to always
    treat it as a pass-through clock, i.e. with a fixed divide of 1, which
    may not be the case. Child clock rates are then recalculated using the
    wrong parent rate.
    
    Therefore instead of dropping the recalc_rate() and round_rate()
    callbacks, alter clk_divider_bestdiv() to always report the current
    divider as the best divider so that it is never altered.
    
    For me the read only clock was the system clock, which divided the PLL
    rate by 2, from which both the UART and the SPI clocks were divided.
    Initial setting of the UART rate set it correctly, but when the SPI
    clock was set, the other child clocks were miscalculated. The UART clock
    was recalculated using the PLL rate as the parent rate, resulting in a
    UART new_rate of double what it should be, and a UART which spewed forth
    garbage when the rate changes were propagated.
    Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
    Cc: Thomas Abraham <thomas.ab@samsung.com>
    Cc: Tomasz Figa <t.figa@samsung.com>
    Cc: Max Schwarz <max.schwarz@online.de>
    Cc: <stable@vger.kernel.org> # v3.16+
    Acked-by: default avatarHaojian Zhuang <haojian.zhuang@gmail.com>
    Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
    e6d5e7d9
clk-divider.c 11.9 KB