Enable PCIe0 (Wi-Fi) and 2 (SDX55m) interfaces and PHYs and assign relevant
pins and regulators.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616122708.144770-3-konrad.dybcio@somainline.orgSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>