• Suketu Shah's avatar
    drm/i915/skl: Add DC5 Trigger Sequence · dc174300
    Suketu Shah authored
    Add triggers as per expectations mentioned in gen9_enable_dc5
    and gen9_disable_dc5 patch.
    
    Also call POSTING_READ for every write to a register to ensure that
    its written immediately.
    
    v1: Remove POSTING_READ calls as they've already been added in previous patches.
    
    v2: Rebase to move all runtime pm specific changes to intel_runtime_pm.c file.
    
    Modified as per review comments from Imre:
    1] Change variable name 'dc5_allowed' to 'dc5_enabled' to correspond to relevant
       functions.
    2] Move the check dc5_enabled in skl_set_power_well() to disable DC5 into
       gen9_disable_DC5 which is a more appropriate place.
    3] Convert checks for 'pm.dc5_enabled' and 'pm.suspended' in skl_set_power_well()
       to warnings. However, removing them for now as they'll be included in a future patch
       asserting DC-state entry/exit criteria.
    4] Enable DC5, only when CSR firmware is verified to be loaded. Create new structure
       to track 'enabled' and 'deferred' status of DC5.
    5] Ensure runtime PM reference is obtained, if CSR is not loaded, to avoid entering
       runtime-suspend and release it when it's loaded.
    6] Protect necessary CSR-related code with locks.
    7] Move CSR-loading call to runtime PM initialization, as power domains needed to be
       accessed during deferred DC5-enabling, are not initialized earlier.
    
    v3: Rebase to latest.
    
    Modified as per review comments from Imre:
    1] Use blocking wait for CSR-loading to finish to enable DC5  for simplicity, instead of
       deferring enabling DC5 until CSR is loaded.
    2] Obtain runtime PM reference during CSR-loading initialization itself as deferred DC5-
       enabling is removed and release it at the end of CSR-loading functionality.
    3] Revert calling CSR-loading functionality to the beginning of i915 driver-load
       functionality to avoid any delay in loading.
    4] Define another variable to track whether CSR-loading failed and use it to avoid enabling
       DC5 if it's true.
    5] Define CSR-load-status accessor functions for use later.
    
    v4:
    1] Disable DC5 before enabling PG2 instead of after it.
    2] DC5 was being mistaken enabled even when CSR-loading timed-out. Fix that.
    3] Enable DC5-related functionality using a macro.
    4] Remove dc5_enabled tracking variable and its use as it's not needed now.
    
    v5:
    1] Mark CSR failed to load where necessary in finish_csr_load function.
    2] Use mutex-protected accessor function to check if CSR loaded instead of directly
       accessing the variable.
    3] Prefix csr_load_status_get/set function names with intel_.
    
    v6: rebase to latest.
    v7: Rebase on top of nightly (Damien)
    v8: Squashed the patch from Imre - added csr helper pointers to simplify the code. (Imre)
    v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
    v10: Added a enum for different csr states, suggested by Imre. (Animesh)
    
    v11: Based on review comments from Imre, Damien and Daniel following changes done
    - enum name chnaged to csr_state (singular form).
    - FW_UNINITIALIZED used as zeroth element in enum csr_state.
    - Prototype changed for helper function(set/get csr status), using enum csr_state instead of bool.
    
    v12: Based on review comment from Imre, introduced bool fw_loaded local to finish_csr_load() which helps
    calling once to set the csr status. The same flag used to fail RPM if find any issue during
    firmware loading.
    
    Issue: VIZ-2819
    Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
    Signed-off-by: default avatarSuketu Shah <suketu.j.shah@intel.com>
    Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
    Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
    Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    dc174300
intel_csr.c 10.4 KB