• Sergei Shtylyov's avatar
    clk: renesas: rcar-gen3: Add RPC clocks · db4a0073
    Sergei Shtylyov authored
    The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all
    the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field
    is different between SoCs; it makes sense to support the most common case
    of this encoding in the R-Car gen3 CPG driver...
    
    After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from
    it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except
    V3M (R8A77970); the composite clock driver seems handy for this task, using
    the spinlock added in the previous patch...
    Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
    Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
    db4a0073
rcar-gen3-cpg.c 18.4 KB