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David Clear authored
The Micron mt25qu02g supports both x2 and x4 transactions. Add the SPI_NOR_DUAL_READ flag to its spi_nor_ids[] table entry. Tested on Pensando SoC hardware with a cadence quadspi controller via drivers/spi/spi-cadence-quadspi.c, in x2 mode at 50MHz. - random data write, erase, read - verified erase operations - random data write, read/compare - verified write/read operations Signed-off-by:
David Clear <dac2@pensando.io> Acked-by:
Shannon Nelson <snelson@pensando.io> Link: https://lore.kernel.org/r/20200720163656.38006-3-dac2@pensando.ioSigned-off-by:
Tudor Ambarus <tudor.ambarus@microchip.com>
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