• Michel Thierry's avatar
    drm/i915: Consider HW CSB write pointer before resetting the sw read pointer · dfc53c5e
    Michel Thierry authored
    A previous commit resets the Context Status Buffer (CSB) read pointer in
    ring init
        commit c0a03a2e ("drm/i915: Reset CSB read pointer in ring init")
    
    This is generally correct, but this pointer is not reset after
    suspend/resume in some platforms (cht). In this case, the driver should
    read the register value instead of resetting the sw read counter to 0.
    Otherwise we process old events, leading to unwanted pre-emptions or
    something worse.
    
    But in other platforms (bdw) and also during GPU reset or power up, the
    CSBWP is reset to 0x7 (an invalid number), and in this case the read
    pointer should be set to 5 (the interrupt code will increment this
    counter one more time, and will start reading from CSB[0]).
    
    v2: When the CSB registers are reset, the read pointer needs to be set
    to 5, otherwise the first write (CSB[0]) won't be read (Mika).
    Replace magic numbers with GEN8_CSB_ENTRIES (6) and GEN8_CSB_PTR_MASK
    (0x07).
    
    Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
    Cc: stable@vger.kernel.org # v4.0+
    Signed-off-by: default avatarLei Shen <lei.shen@intel.com>
    Signed-off-by: default avatarDeepak S <deepak.s@intel.com>
    Signed-off-by: default avatarMichel Thierry <michel.thierry@intel.com>
    Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
    Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
    dfc53c5e
intel_lrc.c 73.3 KB