• Ionela Voinescu's avatar
    arm64: errata: add detection for AMEVCNTR01 incrementing incorrectly · e89d120c
    Ionela Voinescu authored
    The AMU counter AMEVCNTR01 (constant counter) should increment at the same
    rate as the system counter. On affected Cortex-A510 cores, AMEVCNTR01
    increments incorrectly giving a significantly higher output value. This
    results in inaccurate task scheduler utilization tracking and incorrect
    feedback on CPU frequency.
    
    Work around this problem by returning 0 when reading the affected counter
    in key locations that results in disabling all users of this counter from
    using it either for frequency invariance or as FFH reference counter. This
    effect is the same to firmware disabling affected counters.
    
    Details on how the two features are affected by this erratum:
    
     - AMU counters will not be used for frequency invariance for affected
       CPUs and CPUs in the same cpufreq policy. AMUs can still be used for
       frequency invariance for unaffected CPUs in the system. Although
       unlikely, if no alternative method can be found to support frequency
       invariance for affected CPUs (cpufreq based or solution based on
       platform counters) frequency invariance will be disabled. Please check
       the chapter on frequency invariance at
       Documentation/scheduler/sched-capacity.rst for details of its effect.
    
     - Given that FFH can be used to fetch either the core or constant counter
       values, restrictions are lifted regarding any of these counters
       returning a valid (!0) value. Therefore FFH is considered supported
       if there is a least one CPU that support AMUs, independent of any
       counters being disabled or affected by this erratum. Clarifying
       comments are now added to the cpc_ffh_supported(), cpu_read_constcnt()
       and cpu_read_corecnt() functions.
    
    The above is achieved through adding a new erratum: ARM64_ERRATUM_2457168.
    Signed-off-by: default avatarIonela Voinescu <ionela.voinescu@arm.com>
    Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    Cc: Catalin Marinas <catalin.marinas@arm.com>
    Cc: Will Deacon <will@kernel.org>
    Cc: James Morse <james.morse@arm.com>
    Link: https://lore.kernel.org/r/20220819103050.24211-1-ionela.voinescu@arm.comSigned-off-by: default avatarWill Deacon <will@kernel.org>
    e89d120c
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