• Ben Widawsky's avatar
    drm/i915: ring irq cleanups · e2a1e2f0
    Ben Widawsky authored
    - gen6 put/get only need one argument
        rflags and gflags are always the same (see above explanation)
    - remove a couple redundantly defined IRQs
    - reordered some lines to make things go in descending order
    
    Every ring has its own interrupts, enables, masks, and status bits that
    are fed into the main interrupt enable/mask/status registers. At one
    point in time it seemed like a good idea to make our functions support
    the notion that each interrupt may have a different bit position in the
    corresponding register (blitter parser error may be bit n in IMR, but
    bit m in blitter IMR). It turned out though that the HW designers did us
    a solid on Gen6+ and this unfortunate situation has been avoided. This
    allows our interrupt code to be cleaned up a bit.
    
    I jammed this into one commit because there should be no functional
    change with this commit, and staging it into multiple commits was
    unnecessarily artificial IMO.
    
    CC: Chris Wilson <chris@chris-wilson.co.uk>
    CC: Jesse Barnes <jbarnes@virtuousgeek.org>
    Signed-off-by: default avatarBen Widawsky <benjamin.widawsky@intel.com>
    Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    [danvet:
    - fixed up merged conflict with vlv changes.
    - added GEN6 to GT blitter bit, we only use it on gen6+.
    - added a comment to both ring irq bits and GT irq bits that on gen6+
      these alias.
    - added comment that GT_BSD_USER_INTERRUPT is ilk-only.
    - I've got confused a bit that we still use GT_USER_INTERRUPT on ivb
      for the render ring - but this goes back to ilk where we have only
      gt interrupt bits and so we be equally confusing if changed.]
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    e2a1e2f0
i915_irq.c 68.8 KB