-
Rajendra Nayak authored
The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL register are 3 bits wide. Fix the MASK definition accordingly. Signed-off-by:
Rajendra Nayak <rnayak@ti.com> Signed-off-by:
Paul Walmsley <paul@pwsan.com>
4e68f5a7