• Dave Hansen's avatar
    x86/mm: Disallow running with 32-bit PTEs to work around erratum · e4a84be6
    Dave Hansen authored
    The Intel(R) Xeon Phi(TM) Processor x200 Family (codename: Knights
    Landing) has an erratum where a processor thread setting the Accessed
    or Dirty bits may not do so atomically against its checks for the
    Present bit.  This may cause a thread (which is about to page fault)
    to set A and/or D, even though the Present bit had already been
    atomically cleared.
    
    These bits are truly "stray".  In the case of the Dirty bit, the
    thread associated with the stray set was *not* allowed to write to
    the page.  This means that we do not have to launder the bit(s); we
    can simply ignore them.
    
    If the PTE is used for storing a swap index or a NUMA migration index,
    the A bit could be misinterpreted as part of the swap type.  The stray
    bits being set cause a software-cleared PTE to be interpreted as a
    swap entry.  In some cases (like when the swap index ends up being
    for a non-existent swapfile), the kernel detects the stray value
    and WARN()s about it, but there is no guarantee that the kernel can
    always detect it.
    
    When we have 64-bit PTEs (64-bit mode or 32-bit PAE), we were able
    to move the swap PTE format around to avoid these troublesome bits.
    But, 32-bit non-PAE is tight on bits.  So, disallow it from running
    on this hardware.  I can't imagine anyone wanting to run 32-bit
    non-highmem kernels on this hardware, but disallowing them from
    running entirely is surely the safe thing to do.
    Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
    Cc: Andrew Morton <akpm@linux-foundation.org>
    Cc: Andy Lutomirski <luto@kernel.org>
    Cc: Borislav Petkov <bp@alien8.de>
    Cc: Brian Gerst <brgerst@gmail.com>
    Cc: Dave Hansen <dave@sr71.net>
    Cc: Denys Vlasenko <dvlasenk@redhat.com>
    Cc: H. Peter Anvin <hpa@zytor.com>
    Cc: Josh Poimboeuf <jpoimboe@redhat.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Luis R. Rodriguez <mcgrof@suse.com>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Toshi Kani <toshi.kani@hp.com>
    Cc: dave.hansen@intel.com
    Cc: linux-mm@kvack.org
    Cc: mhocko@suse.com
    Link: http://lkml.kernel.org/r/20160708001914.D0B50110@viggo.jf.intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
    e4a84be6
cpu.c 2.05 KB