• Huacai Chen's avatar
    MIPS: Add Loongson-3B support · e7841be5
    Huacai Chen authored
    Loongson-3B is a 8-cores processor. In general it looks like there are
    two Loongson-3A integrated in one chip: 8 cores are separated into two
    groups (two NUMA node), each node has its own local memory.
    
    Of course there are some differences between one Loongson-3B and two
    Loongson-3A. E.g., the base addresses of IPI registers of each node are
    not the same; Loongson-3A use ChipConfig register to enable/disable
    clock, but Loongson-3B use FreqControl register instead.
    
    There are two revision of Loongson-3B, the first revision is called as
    Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the
    second revision is called as Loongson-3B1500, whose frequency is 1.5GHz
    and has a PRid 0x6307. Both revisions has a bug that clock cannot be
    disabled at runtime, but this will be fixed in future.
    Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
    Cc: John Crispin <john@phrozen.org>
    Cc: Steven J. Hill <Steven.Hill@imgtec.com>
    Cc: Aurelien Jarno <aurelien@aurel32.net>
    Cc: linux-mips@linux-mips.org
    Cc: Fuxin Zhang <zhangfx@lemote.com>
    Cc: Zhangjin Wu <wuzhangjin@gmail.com>
    Patchwork: https://patchwork.linux-mips.org/patch/7188/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
    e7841be5
loongson.h 12.2 KB