• Philipp Zabel's avatar
    drm/imx: add deferred plane disabling · eb8c8880
    Philipp Zabel authored
    The DP (display processor) channel disable code tried to busy wait for
    the DP sync flow end interrupt status bit when disabling the partial
    plane without a full modeset. That never worked reliably, and it was
    disabled completely by the recent "gpu: ipu-v3: remove IRQ dance on DC
    channel disable" patch, causing ipu_wait_interrupt to always time out
    after 50 ms, which in turn would trigger a timeout in
    drm_atomic_helper_wait_for_vblanks.
    
    This patch changes ipu_plane_atomic_disable to only queue a DP channel
    register update at the next frame boundary and set a flag, which can be
    done without any waiting whatsoever. The imx_drm_atomic_commit_tail then
    calls a new ipu_plane_disable_deferred function that does the actual
    IDMAC teardown of the planes that are flagged for deferred disabling,
    after waiting for the vblank.
    Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
    Reviewed-by: default avatarLucas Stach <l.stach@pengutronix.de>
    eb8c8880
ipu-dp.c 8.12 KB