• Jack Steiner's avatar
    [PATCH] x86-64: - Ignore long SMI interrupts in clock calibration · ed5316d4
    Jack Steiner authored
    Ensure that no SMI interrupts occur between the read of the HPET & TSC
    in the clock calibration loop.
    
    I noticed that a 2.66GHz system incorrectly detected the processor
    clock speed about 1/7 of the time:
    
    	time.c: Detected 2660.005 MHz processor.	(most of the time)
    	time.c: Detected 2988.203 MHz processor.	(sometime)
    
    The problem is caused by an SMI interrupt occuring in hpet_calibrate_tsc()
    between the read of the HPET & TSC. Prior to switching the BIOS into
    ACPI mode, it appears that every 27msec an SMI interrupt occurs. The
    SMI interrupt takes 4.8 msec to process.
    
    Note: On my test system, TICK_MIN had to be >380. I picked 5000
    to minimize risk of having a value that is too small for other
    platforms.
    Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
    Signed-off-by: default avatarAndi Kleen <ak@suse.de>
    
     arch/x86_64/kernel/time.c |   25 +++++++++++++++++++++----
     1 file changed, 21 insertions(+), 4 deletions(-)
    ed5316d4
time.c 34 KB