• Paul Burton's avatar
    irqchip/mips-gic: Use the correct local interrupt map registers · 6d4d367d
    Paul Burton authored
    The MIPS GIC contains a block of registers used to map local interrupts
    to a particular CPU interrupt pin. Since these registers are found at a
    consecutive range of addresses we access them using an index, via the
    (read|write)_gic_v[lo]_map accessor functions. We currently use values
    from enum mips_gic_local_interrupt as those indices.
    
    Unfortunately whilst enum mips_gic_local_interrupt provides the correct
    offsets for bits in the pending & mask registers, the ordering of the
    map registers is subtly different... Compared with the ordering of
    pending & mask bits, the map registers move the FDC from the end of the
    list to index 3 after the timer interrupt. As a result the performance
    counter & software interrupts are therefore at indices 4-6 rather than
    indices 3-5.
    
    Notably this causes problems with performance counter interrupts being
    incorrectly mapped on some systems, and presumably will also cause
    problems for FDC interrupts.
    
    Introduce a function to map from enum mips_gic_local_interrupt to the
    index of the corresponding map register, and use it to ensure we access
    the map registers for the correct interrupts.
    Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
    Fixes: a0dc5cb5 ("irqchip: mips-gic: Simplify gic_local_irq_domain_map()")
    Fixes: da61fcf9 ("irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs")
    Reported-and-tested-by: default avatarArcher Yan <ayan@wavecomp.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Jason Cooper <jason@lakedaemon.net>
    Cc: stable@vger.kernel.org # v4.14+
    Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    6d4d367d
irq-mips-gic.c 19.9 KB