For P4 model < 2, The MSR_FBC_REGISTER_ID ratio is undefined.
Revert the commit that was added to handle that case,
as it results in random MHz displayed.  Something else will
have to be done to properly handle model < 2.

//commit 3e4159ab35c88aef5e063ba78796b277b762a30a
//Author: matthias.christian <matthias.christian>
//Date:   Sat Feb 5 23:09:38 2005 +0000
//
//    [PATCH] speedstep-lib.c: fix frequency multiplier for Pentium4 models 0&1
//
//    The Pentium4 models 0&1 have a longer MSR_EBC_FREQUENCY_ID register as the
//    models 2&3, so the bit shift must be bigger.
//
//    Signed-off-by: Matthias-Christian Ott <matthias.christian@tiscali.de>
//    Signed-off-by: Dominik Brodowski <linux@brodo.de>
//    Signed-off-by: Andrew Morton <akpm@osdl.org>
//    Signed-off-by: Linus Torvalds <torvalds@osdl.org>
//
//    BKrev: 42055232eWM-NgjhZVir44mp5GXktQ

http://bugzilla.kernel.org/show_bug.cgi?id=7186Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>