• Kishon Vijay Abraham I's avatar
    PCI: designware: Program ATU with untranslated address · f4c55c5a
    Kishon Vijay Abraham I authored
    In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see
    only 28-bit addresses.  So whenever the CPU issues a read/write request,
    the 4 most significant bits are used by L3 to determine the target
    controller.  For example, the CPU reserves [mem 0x20000000-0x2fffffff]
    for the PCIe controller but the PCIe controller will see only
    [0x00000000-0x0fffffff].  For programming the outbound translation
    window the *base* should be programmed as 0x00000000.  Whenever we try to
    write to, e.g., 0x20000000, it will be translated to whatever we have
    programmed in the translation window with base as 0x00000000.
    
    This is needed when the dt node is modelled something like this:
    
        axi {
            compatible = "simple-bus";
            #size-cells = <1>;
            #address-cells = <1>;
            ranges = <0x0        0x20000000 0x10000000 // 28-bit bus
                      0x51000000 0x51000000 0x3000>;
            pcie@51000000 {
                    reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>;
                    reg-names = "config", "ti_conf", "rc_dbics";
                    #address-cells = <3>;
                    #size-cells = <2>;
                    ranges = <0x81000000 0 0          0x03000 0 0x00010000
                              0x82000000 0 0x20013000 0x13000 0 0xffed000>;
            };
        };
    
    Here the CPU address for configuration space is 0x20013000 and the
    controller address for configuration space is 0x13000.  The controller
    address should be used while programming the ATU (in order for translation
    to happen properly in DRA7xx).
    Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
    Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
    Reviewed-by: default avatarMohit Kumar <mohit.kumar@st.com>
    Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
    Cc: Jingoo Han <jg1.han@samsung.com>
    Cc: Marek Vasut <marex@denx.de>
    Cc: Arnd Bergmann <arnd@arndb.de>
    f4c55c5a
pcie-designware.h 2.18 KB