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Biao Huang authored
1. the frequency of csr clock is 66.5MHz, so the csr_clk value should be 0 other than 5. 2. the csr_clk can be got from device tree, so remove initialization here. Fixes: 9992f37e ("stmmac: dwmac-mediatek: add support for mt2712") Signed-off-by:
Biao Huang <biao.huang@mediatek.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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