• Maxime Ripard's avatar
    clk: sunxi: Add a driver for the PLL2 · 460d0d44
    Maxime Ripard authored
    The PLL2 on the A10 and later SoCs is the clock used for all the audio
    related operations.
    
    This clock has a somewhat complex output tree, with three outputs (2X, 4X
    and 8X) with a fixed divider from the base clock, and an output (1X) with a
    post divider.
    
    However, we can simplify things since the 1X divider can be fixed, and we
    end up by having a base clock not exposed to any device (or at least
    directly, since the 4X output doesn't have any divider), and 4 fixed
    divider clocks that will be exposed.
    
    This clock seems to have been introduced, at least in this form, in the
    revision B of the A10, but we don't have any information on the clock used
    on the revision A.
    Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
    Reviewed-by: default avatarChen-Yu Tsai <wens@csie.org>
    460d0d44
sun4i-a10-pll2.h 2.23 KB