• Daniel Vetter's avatar
    drm/i915: Support pf CRC source on haswell transcoder edp · fabf6e51
    Daniel Vetter authored
    The always-on power well pixel path on haswell is routed such that it
    bypasses the panel fitter when we use is. Which means the pfit CRC
    source won't work in that configuration.
    
    Add a new disallow-bypass flags to the pfit pipe config state and set
    it when we want to use the pf CRC. Results in a bit of flicker, but
    should get the job done. We'll also undo do it afterwards to make sure
    other tests arent' negatively affected.
    
    Totally untested due to lack of hsw laptops around here.
    
    v2: s/disallow_bypass/force_power_well_on/ to avoid a double negative
    (Damien).
    
    v3: force_thru because roadsigns.
    
    v4: Don't forget the power wells! Also note that until the runtime pm
    for DPMS series is fully merged the simple disable/enable trick won't
    work since the ->crtc_mode_set callback is still required to do nasty
    things. This stuff is tricky, but I think by both fixing up
    get_crtc_power_domains and the debugfs wa code we should always
    grab/drop the additional power well correctly.
    
    v5: Wrap in () as suggested by Damien to avoid setting reserved values
    for the edp transcoder path on bdw+
    
    References: https://bugs.freedesktop.org/show_bug.cgi?id=72864
    Cc: Damien Lespiau <damien.lespiau@intel.com>
    Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
    Tested-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    fabf6e51
intel_display.c 365 KB