• Alexandru Gagniuc's avatar
    spi: sun4i: Allow transfers larger than FIFO size · 19673791
    Alexandru Gagniuc authored
    SPI transfers were limited to one FIFO depth, which is 64 bytes.
    This was an artificial limitation, however, as the hardware can handle
    much larger bursts. To accommodate this, we enable the interrupt when
    the Rx FIFO is 3/4 full, and drain the FIFO within the interrupt
    handler. The 3/4 ratio was chosen arbitrarily, with the intention to
    reduce the potential number of interrupts.
    
    Since the SUN4I_CTL_TP bit is set, the hardware will pause
    transmission whenever the FIFO is full, so there is no risk of losing
    data if we can't service the interrupt in time.
    
    For the Tx side, enable and use the Tx FIFO 3/4 empty interrupt to
    replenish the FIFO on large SPI bursts. This requires more care in
    when the interrupt is left enabled, as this interrupt will continually
    trigger when the FIFO is less than 1/4 full, even though we
    acknowledge it.
    Signed-off-by: default avatarAlexandru Gagniuc <mr.nuke.me@gmail.com>
    Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
    Signed-off-by: default avatarOlliver Schinagl <o.schinagl@ultimaker.com>
    Signed-off-by: default avatarMark Brown <broonie@kernel.org>
    19673791
spi-sun4i.c 13.8 KB