• Paolo Bonzini's avatar
    KVM: lapic: sync highest ISR to hardware apic on EOI · fc57ac2c
    Paolo Bonzini authored
    When Hyper-V enlightenments are in effect, Windows prefers to issue an
    Hyper-V MSR write to issue an EOI rather than an x2apic MSR write.
    The Hyper-V MSR write is not handled by the processor, and besides
    being slower, this also causes bugs with APIC virtualization.  The
    reason is that on EOI the processor will modify the highest in-service
    interrupt (SVI) field of the VMCS, as explained in section 29.1.4 of
    the SDM; every other step in EOI virtualization is already done by
    apic_send_eoi or on VM entry, but this one is missing.
    
    We need to do the same, and be careful not to muck with the isr_count
    and highest_isr_cache fields that are unused when virtual interrupt
    delivery is enabled.
    
    Cc: stable@vger.kernel.org
    Reviewed-by: default avatarYang Zhang <yang.z.zhang@intel.com>
    Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
    fc57ac2c
lapic.c 46.9 KB