• Ben Skeggs's avatar
    drm/nouveau/pm: calculate memory timings at perflvl creation time · fd99fd61
    Ben Skeggs authored
    Statically generating the PFB register and MR values for each timing set
    turns out to be insufficient.  There's at least one (so far) known piece
    of information which effects MR values which is stored in the perflvl
    entry on some chipsets (and in another table on later ones), which is
    disconnected from the timing table entries.
    
    After this change we will generate a timing set based on an input clock
    frequency instead, and have this data stored in the performance level
    data.
    Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
    Signed-off-by: default avatarMartin Peres <martin.peres@labri.fr>
    fd99fd61
nouveau_pm.h 3.52 KB