• Vineet Gupta's avatar
    ARCv2: mm: THP support · fe6c1b86
    Vineet Gupta authored
    MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
    support.
    
    Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
    new bit "SZ" in TLB page desciptor to distinguish between them.
    Super Page size is configurable in hardware (4K to 16M), but fixed once
    RTL builds.
    
    The exact THP size a Linx configuration will support is a function of:
     - MMU page size (typical 8K, RTL fixed)
     - software page walker address split between PGD:PTE:PFN (typical
       11:8:13, but can be changed with 1 line)
    
    So for above default, THP size supported is 8K * 256 = 2M
    
    Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
    reduces to 1 level (as PTE is folded into PGD and canonically referred
    to as PMD).
    
    Thus thp PMD accessors are implemented in terms of PTE (just like sparc)
    Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
    fe6c1b86
tlbex.S 12 KB