Add gpio-ranges properties to the gpio controller nodes.

These gpio-ranges were created based on "Table 9-10. CONTROL_MODULE
REGISTERS" in the  "AM335x Technical Reference Manual" [0] and "Table
4-2. Pin Attributes" in the "AM335x Sitara Processor datasheet" [1].
A csv file with this data is available for reference [2].

These mappings are valid for all SoC's that are using am33xx-l4.dtsi.
In addition, the only TI AM33xx parts that actually exist are [0]:
AM3351, AM3352, AM3354, AM3356, AM3357, AM3358, AM3359

These gpio-ranges properties should be added as they describe the
relationship between a gpio line and pin control register that exists
in the hardware.  For example, GPMC_A0 pin has mode 7 which is labeled
gpio1_16. conf_gpmc_a0 register is at offset 840h which makes it pin 16.

[0] https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
[1] http://www.ti.com/lit/ds/symlink/am3358.pdf
[2] https://gist.github.com/pdp7/6ffaddc8867973c1c3e8612cfaf72020
[3] http://www.ti.com/processors/sitara-arm/am335x-cortex-a8/overview.htmlSigned-off-by: Drew Fustini <drew@beagleboard.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>