• Felipe Balbi's avatar
    usb: dwc3: core: improve reset sequence · f59dcab1
    Felipe Balbi authored
    According to Synopsys Databook, we shouldn't be
    relying on GCTL.CORESOFTRESET bit as that's only for
    debugging purposes. Instead, let's use DCTL.CSFTRST
    if we're OTG or PERIPHERAL mode.
    
    Host side block will be reset by XHCI driver if
    necessary. Note that this reduces amount of time
    spent on dwc3_probe() by a long margin.
    
    We're still gonna wait for reset to finish for a
    long time (default to 1ms max), but tests show that
    the reset polling loop executed at most 19 times
    (modprobe dwc3 && modprobe -r dwc3 executed 1000
    times in a row).
    Suggested-by: default avatarMian Yousaf Kaukab <yousaf.kaukab@intel.com>
    Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
    f59dcab1
core.c 30.3 KB