Commit 0003417d authored by Faiz Abbas's avatar Faiz Abbas Committed by Ulf Hansson

mmc: sdhci_am654: Update delay chain configuration

For speed modes where DLL is not enabled write to TXDLYCLK to enable
transmitter delay chain mode.
Signed-off-by: default avatarFaiz Abbas <faiz_abbas@ti.com>
Link: https://lore.kernel.org/r/20200619125801.9530-6-faiz_abbas@ti.comSigned-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent fe52e2fb
...@@ -61,6 +61,8 @@ ...@@ -61,6 +61,8 @@
#define CALDONE_MASK BIT(CALDONE_SHIFT) #define CALDONE_MASK BIT(CALDONE_SHIFT)
#define RETRIM_SHIFT 17 #define RETRIM_SHIFT 17
#define RETRIM_MASK BIT(RETRIM_SHIFT) #define RETRIM_MASK BIT(RETRIM_SHIFT)
#define SELDLYTXCLK_SHIFT 17
#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
#define DRIVER_STRENGTH_50_OHM 0x0 #define DRIVER_STRENGTH_50_OHM 0x0
#define DRIVER_STRENGTH_33_OHM 0x1 #define DRIVER_STRENGTH_33_OHM 0x1
...@@ -228,8 +230,14 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) ...@@ -228,8 +230,14 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) {
regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
SELDLYTXCLK_MASK, 0);
sdhci_am654_setup_dll(host, clock); sdhci_am654_setup_dll(host, clock);
} else {
regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT);
}
} }
static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
......
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