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Commit 00d79e9d authored by Hans J. Koch's avatar Hans J. Koch
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arm: Remove mach-tcc8k directory 

The Telechips ARM architecture is being removed. This patch
deletes the arch/arm/mach-tcc8k/ folder.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Harry Sievers <hsievers@csselectronic.com>
Signed-off-by: default avatarHans J. Koch <hjk@hansjkoch.de>
parent 273b5e51
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arch/arm/mach-tcc8k/Kconfig deleted 100644 → 0
View file @ 273b5e51
if ARCH_TCC8K
comment "TCC8000 systems:"
config MACH_TCC8000_SDK
bool "Telechips TCC8000-SDK development kit"
default y
help
Support for the Telechips TCC8000-SDK board.
endif
arch/arm/mach-tcc8k/Makefile deleted 100644 → 0
View file @ 273b5e51
#
# Makefile for TCC8K boards and common files.
#
# Common support
obj-y += clock.o irq.o time.o io.o devices.o
# Board specific support
obj-$(CONFIG_MACH_TCC8000_SDK) += board-tcc8000-sdk.o
arch/arm/mach-tcc8k/Makefile.boot deleted 100644 → 0
View file @ 273b5e51
zreladdr-y += 0x20008000
params_phys-y := 0x20000100
initrd_phys-y := 0x20800000
arch/arm/mach-tcc8k/board-tcc8000-sdk.c deleted 100644 → 0
View file @ 273b5e51
/*
* Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/clock.h>
#include <mach/tcc-nand.h>
#include <mach/tcc8k-regs.h>
#include "common.h"
#define XI_FREQUENCY 12000000
#define XTI_FREQUENCY 32768
#ifdef CONFIG_MTD_NAND_TCC
/* NAND */
static struct tcc_nand_platform_data tcc8k_sdk_nand_data = {
.width = 1,
.hw_ecc = 0,
};
#endif
static void __init tcc8k_init(void)
{
#ifdef CONFIG_MTD_NAND_TCC
tcc_nand_device.dev.platform_data = &tcc8k_sdk_nand_data;
platform_device_register(&tcc_nand_device);
#endif
}
static void __init tcc8k_init_timer(void)
{
tcc_clocks_init(XI_FREQUENCY, XTI_FREQUENCY);
}
static struct sys_timer tcc8k_timer = {
.init = tcc8k_init_timer,
};
static void __init tcc8k_map_io(void)
{
tcc8k_map_common_io();
/* set PLL0 clock to 96MHz, adapt UART0 divisor */
__raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS);
__raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS);
/* set PLL1 clock to 192MHz */
__raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS);
/* set PLL2 clock to 48MHz */
__raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS);
/* with CPU freq higher than 150 MHz, need extra DTCM wait */
__raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS);
/* PLL locking time as specified */
udelay(300);
}
MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
.atag_offset = 0x100,
.map_io = tcc8k_map_io,
.init_irq = tcc8k_init_irq,
.init_machine = tcc8k_init,
.timer = &tcc8k_timer,
MACHINE_END
arch/arm/mach-tcc8k/clock.c deleted 100644 → 0
View file @ 273b5e51
This diff is collapsed.
arch/arm/mach-tcc8k/common.h deleted 100644 → 0
View file @ 273b5e51
#ifndef MACH_TCC8K_COMMON_H
#define MACH_TCC8K_COMMON_H
#include <linux/platform_device.h>
extern struct platform_device tcc_nand_device;
struct clk;
extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq);
extern void tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq);
extern void tcc8k_init_irq(void);
extern void tcc8k_map_common_io(void);
#endif
arch/arm/mach-tcc8k/devices.c deleted 100644 → 0
View file @ 273b5e51
/*
* linux/arch/arm/mach-tcc8k/devices.c
*
* Copyright (C) Telechips, Inc.
* Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
*
* Licensed under the terms of GPL v2.
*
*/
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/mach/map.h>
#include <mach/tcc8k-regs.h>
#include <mach/irqs.h>
#include "common.h"
static u64 tcc8k_dmamask = DMA_BIT_MASK(32);
#ifdef CONFIG_MTD_NAND_TCC
/* NAND controller */
static struct resource tcc_nand_resources[] = {
{
.start = (resource_size_t)NFC_BASE,
.end = (resource_size_t)NFC_BASE + 0x7f,
.flags = IORESOURCE_MEM,
}, {
.start = INT_NFC,
.end = INT_NFC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device tcc_nand_device = {
.name = "tcc_nand",
.id = 0,
.num_resources = ARRAY_SIZE(tcc_nand_resources),
.resource = tcc_nand_resources,
};
#endif
#ifdef CONFIG_MMC_TCC8K
/* MMC controller */
static struct resource tcc8k_mmc0_resource[] = {
{
.start = INT_SD0,
.end = INT_SD0,
.flags = IORESOURCE_IRQ,
},
};
static struct resource tcc8k_mmc1_resource[] = {
{
.start = INT_SD1,
.end = INT_SD1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device tcc8k_mmc0_device = {
.name = "tcc-mmc",
.id = 0,
.num_resources = ARRAY_SIZE(tcc8k_mmc0_resource),
.resource = tcc8k_mmc0_resource,
.dev = {
.dma_mask = &tcc8k_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
struct platform_device tcc8k_mmc1_device = {
.name = "tcc-mmc",
.id = 1,
.num_resources = ARRAY_SIZE(tcc8k_mmc1_resource),
.resource = tcc8k_mmc1_resource,
.dev = {
.dma_mask = &tcc8k_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
}
};
static inline void tcc8k_init_mmc(void)
{
u32 reg = __raw_readl(GPIOPS_BASE + GPIOPS_FS1_OFFS);
reg |= GPIOPS_FS1_SDH0_BITS | GPIOPS_FS1_SDH1_BITS;
__raw_writel(reg, GPIOPS_BASE + GPIOPS_FS1_OFFS);
platform_device_register(&tcc8k_mmc0_device);
platform_device_register(&tcc8k_mmc1_device);
}
#else
static inline void tcc8k_init_mmc(void) { }
#endif
#ifdef CONFIG_USB_OHCI_HCD
static int tcc8k_ohci_init(struct device *dev)
{
u32 reg;
/* Use GPIO PK19 as VBUS control output */
reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS0_OFFS);
reg &= ~(1 << 19);
__raw_writel(reg, GPIOPK_BASE + GPIOPK_FS0_OFFS);
reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS1_OFFS);
reg &= ~(1 << 19);
__raw_writel(reg, GPIOPK_BASE + GPIOPK_FS1_OFFS);
reg = __raw_readl(GPIOPK_BASE + GPIOPK_DOE_OFFS);
reg |= (1 << 19);
__raw_writel(reg, GPIOPK_BASE + GPIOPK_DOE_OFFS);
/* Turn on VBUS */
reg = __raw_readl(GPIOPK_BASE + GPIOPK_DAT_OFFS);
reg |= (1 << 19);
__raw_writel(reg, GPIOPK_BASE + GPIOPK_DAT_OFFS);
return 0;
}
static struct resource tcc8k_ohci0_resources[] = {
[0] = {
.start = (resource_size_t)USBH0_BASE,
.end = (resource_size_t)USBH0_BASE + 0x5c,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_USBH0,
.end = INT_USBH0,
.flags = IORESOURCE_IRQ,
}
};
static struct resource tcc8k_ohci1_resources[] = {
[0] = {
.start = (resource_size_t)USBH1_BASE,
.end = (resource_size_t)USBH1_BASE + 0x5c,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = INT_USBH1,
.end = INT_USBH1,
.flags = IORESOURCE_IRQ,
}
};
static struct tccohci_platform_data tcc8k_ohci0_platform_data = {
.controller = 0,
.port_mode = PMM_PERPORT_MODE,
.init = tcc8k_ohci_init,
};
static struct tccohci_platform_data tcc8k_ohci1_platform_data = {
.controller = 1,
.port_mode = PMM_PERPORT_MODE,
.init = tcc8k_ohci_init,
};
static struct platform_device ohci0_device = {
.name = "tcc-ohci",
.id = 0,
.dev = {
.dma_mask = &tcc8k_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &tcc8k_ohci0_platform_data,
},
.num_resources = ARRAY_SIZE(tcc8k_ohci0_resources),
.resource = tcc8k_ohci0_resources,
};
static struct platform_device ohci1_device = {
.name = "tcc-ohci",
.id = 1,
.dev = {
.dma_mask = &tcc8k_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &tcc8k_ohci1_platform_data,
},
.num_resources = ARRAY_SIZE(tcc8k_ohci1_resources),
.resource = tcc8k_ohci1_resources,
};
static void __init tcc8k_init_usbhost(void)
{
platform_device_register(&ohci0_device);
platform_device_register(&ohci1_device);
}
#else
static void __init tcc8k_init_usbhost(void) { }
#endif
/* USB device controller*/
#ifdef CONFIG_USB_GADGET_TCC8K
static struct resource udc_resources[] = {
[0] = {
.start = INT_USBD,
.end = INT_USBD,
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = INT_UDMA,
.end = INT_UDMA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device tcc8k_udc_device = {
.name = "tcc-udc",
.id = 0,
.resource = udc_resources,
.num_resources = ARRAY_SIZE(udc_resources),
.dev = {
.dma_mask = &tcc8k_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static void __init tcc8k_init_usb_gadget(void)
{
platform_device_register(&tcc8k_udc_device);
}
#else
static void __init tcc8k_init_usb_gadget(void) { }
#endif /* CONFIG_USB_GADGET_TCC83X */
static int __init tcc8k_init_devices(void)
{
tcc8k_init_mmc();
tcc8k_init_usbhost();
tcc8k_init_usb_gadget();
return 0;
}
arch_initcall(tcc8k_init_devices);
arch/arm/mach-tcc8k/io.c deleted 100644 → 0
View file @ 273b5e51
/*
* linux/arch/arm/mach-tcc8k/io.c
*
* (C) 2009 Hans J. Koch <hjk@linutronix.de>
*
* derived from TCC83xx io.c
* Copyright (C) Telechips, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <asm/mach/map.h>
#include <mach/tcc8k-regs.h>
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
*/
static struct map_desc tcc8k_io_desc[] __initdata = {
{
.virtual = (unsigned long)CS1_BASE_VIRT,
.pfn = __phys_to_pfn(CS1_BASE),
.length = CS1_SIZE,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)AHB_PERI_BASE_VIRT,
.pfn = __phys_to_pfn(AHB_PERI_BASE),
.length = AHB_PERI_SIZE,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)APB0_PERI_BASE_VIRT,
.pfn = __phys_to_pfn(APB0_PERI_BASE),
.length = APB0_PERI_SIZE,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)APB1_PERI_BASE_VIRT,
.pfn = __phys_to_pfn(APB1_PERI_BASE),
.length = APB1_PERI_SIZE,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)EXT_MEM_CTRL_BASE_VIRT,
.pfn = __phys_to_pfn(EXT_MEM_CTRL_BASE),
.length = EXT_MEM_CTRL_SIZE,
.type = MT_DEVICE,
},
};
/*
* Maps common IO regions for tcc8k.
*
*/
void __init tcc8k_map_common_io(void)
{
iotable_init(tcc8k_io_desc, ARRAY_SIZE(tcc8k_io_desc));
}
arch/arm/mach-tcc8k/irq.c deleted 100644 → 0
View file @ 273b5e51
/*
* Copyright (C) Telechips, Inc.
* Copyright (C) 2009-2010 Hans J. Koch <hjk@linutronix.de>
*
* Licensed under the terms of the GNU GPL version 2.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <mach/tcc8k-regs.h>
#include <mach/irqs.h>
#include "common.h"
/* Disable IRQ */
static void tcc8000_mask_ack_irq0(struct irq_data *d)
{
PIC0_IEN &= ~(1 << d->irq);
PIC0_CREQ |= (1 << d->irq);
}
static void tcc8000_mask_ack_irq1(struct irq_data *d)
{
PIC1_IEN &= ~(1 << (d->irq - 32));
PIC1_CREQ |= (1 << (d->irq - 32));
}
static void tcc8000_mask_irq0(struct irq_data *d)
{
PIC0_IEN &= ~(1 << d->irq);
}
static void tcc8000_mask_irq1(struct irq_data *d)
{
PIC1_IEN &= ~(1 << (d->irq - 32));
}
static void tcc8000_ack_irq0(struct irq_data *d)
{
PIC0_CREQ |= (1 << d->irq);
}
static void tcc8000_ack_irq1(struct irq_data *d)
{
PIC1_CREQ |= (1 << (d->irq - 32));
}
/* Enable IRQ */
static void tcc8000_unmask_irq0(struct irq_data *d)
{
PIC0_IEN |= (1 << d->irq);
PIC0_INTOEN |= (1 << d->irq);
}
static void tcc8000_unmask_irq1(struct irq_data *d)
{
PIC1_IEN |= (1 << (d->irq - 32));
PIC1_INTOEN |= (1 << (d->irq - 32));
}
static struct irq_chip tcc8000_irq_chip0 = {
.name = "tcc_irq0",
.irq_mask = tcc8000_mask_irq0,
.irq_ack = tcc8000_ack_irq0,
.irq_mask_ack = tcc8000_mask_ack_irq0,
.irq_unmask = tcc8000_unmask_irq0,
};
static struct irq_chip tcc8000_irq_chip1 = {
.name = "tcc_irq1",
.irq_mask = tcc8000_mask_irq1,
.irq_ack = tcc8000_ack_irq1,
.irq_mask_ack = tcc8000_mask_ack_irq1,
.irq_unmask = tcc8000_unmask_irq1,
};
void __init tcc8k_init_irq(void)
{
int irqno;
/* Mask and clear all interrupts */
PIC0_IEN = 0x00000000;
PIC0_CREQ = 0xffffffff;
PIC1_IEN = 0x00000000;
PIC1_CREQ = 0xffffffff;
PIC0_MEN0 = 0x00000003;
PIC1_MEN1 = 0x00000003;
PIC1_MEN = 0x00000003;
/* let all IRQs be level triggered */
PIC0_TMODE = 0xffffffff;
PIC1_TMODE = 0xffffffff;
/* all IRQs are IRQs (not FIQs) */
PIC0_IRQSEL = 0xffffffff;
PIC1_IRQSEL = 0xffffffff;
for (irqno = 0; irqno < NR_IRQS; irqno++) {
if (irqno < 32)
irq_set_chip(irqno, &tcc8000_irq_chip0);
else
irq_set_chip(irqno, &tcc8000_irq_chip1);
irq_set_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}
arch/arm/mach-tcc8k/time.c deleted 100644 → 0
View file @ 273b5e51
/*
* TCC8000 system timer setup
*
* (C) 2009 Hans J. Koch <hjk@linutronix.de>
*
* Licensed under the terms of the GPL version 2.
*
*/
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <asm/mach/time.h>
#include <mach/tcc8k-regs.h>
#include <mach/irqs.h>
#include "common.h"
static void __iomem *timer_base;
static int tcc_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS);
__raw_writel(reg + evt, timer_base + TC32CMP0_OFFS);
return 0;
}
static void tcc_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
unsigned long tc32irq;
switch (mode) {
case CLOCK_EVT_MODE_ONESHOT:
tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
tc32irq |= TC32IRQ_IRQEN0;
__raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
break;
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_UNUSED:
tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
tc32irq &= ~TC32IRQ_IRQEN0;
__raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
break;
case CLOCK_EVT_MODE_PERIODIC:
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
/* Acknowledge TC32 interrupt by reading TC32IRQ */
__raw_readl(timer_base + TC32IRQ_OFFS);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct clock_event_device clockevent_tcc = {
.name = "tcc_timer1",
.features = CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.set_mode = tcc_set_mode,
.set_next_event = tcc_set_next_event,
.rating = 200,
};
static struct irqaction tcc8k_timer_irq = {
.name = "TC32_timer",
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = tcc8k_timer_interrupt,
.dev_id = &clockevent_tcc,
};
static int __init tcc_clockevent_init(struct clk *clock)
{
unsigned int c = clk_get_rate(clock);
clocksource_mmio_init(timer_base + TC32MCNT_OFFS, "tcc_tc32", c,
200, 32, clocksource_mmio_readl_up);
clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
clockevent_tcc.shift);
clockevent_tcc.max_delta_ns =
clockevent_delta2ns(0xfffffffe, &clockevent_tcc);
clockevent_tcc.min_delta_ns =
clockevent_delta2ns(0xff, &clockevent_tcc);
clockevent_tcc.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_tcc);
return 0;
}
void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq)
{
u32 reg;
timer_base = base;
tcc8k_timer_irq.irq = irq;
/* Enable clocks */
clk_enable(clock);
/* Initialize 32-bit timer */
reg = __raw_readl(timer_base + TC32EN_OFFS);
reg &= ~TC32EN_ENABLE; /* Disable timer */
__raw_writel(reg, timer_base + TC32EN_OFFS);
/* Free running timer, counting from 0 to 0xffffffff */
__raw_writel(0, timer_base + TC32EN_OFFS);
__raw_writel(0, timer_base + TC32LDV_OFFS);
reg = __raw_readl(timer_base + TC32IRQ_OFFS);
reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */
__raw_writel(reg, timer_base + TC32IRQ_OFFS);
__raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS);
tcc_clockevent_init(clock);
setup_irq(irq, &tcc8k_timer_irq);
}
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