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Commit 010eeeac authored by Nicolas Pitre's avatar Nicolas Pitre Committed by Russell King
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[ARM PATCH] 2080/1: clean up io-{read|write}sl 

Patch from Nicolas Pitre

- eliminate difference between ARMv3 and ARMv4 versions of io-readsl
- unified little/big endian support
- misc optimisations

Signed-off-by: Nicolas Pitre
parent 630db1e2
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Showing with 114 additions and 161 deletions
arch/arm/lib/Makefile
View file @ 010eeeac
......@@ -12,12 +12,12 @@ lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
testclearbit.o testsetbit.o uaccess.o getuser.o \
putuser.o ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
ucmpdi2.o udivdi3.o lib1funcs.o div64.o \
io-readsb.o io-writesb.o io-writesl.o
io-readsb.o io-writesb.o io-readsl.o io-writesl.o
ifeq ($(CONFIG_CPU_32v3),y)
lib-y += io-readsw-armv3.o io-writesw-armv3.o io-readsl-armv3.o
lib-y += io-readsw-armv3.o io-writesw-armv3.o
else
lib-y += io-readsw-armv4.o io-writesw-armv4.o io-readsl-armv4.o
lib-y += io-readsw-armv4.o io-writesw-armv4.o
endif
lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o
......
arch/arm/lib/io-readsl-armv4.S deleted 100644 → 0
View file @ 630db1e2
/*
* linux/arch/arm/lib/io-readsl-armv4.S
*
* Copyright (C) 1995-2000 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* Note that some reads can be aligned on half-word boundaries.
*/
ENTRY(__raw_readsl)
teq r2, #0 @ do we have to check for the zero len?
moveq pc, lr
ands ip, r1, #3
bne 2f
subs r2, r2, #4
bmi 1001f
stmfd sp!, {r4, lr}
1000: ldr r3, [r0, #0]
ldr r4, [r0, #0]
ldr ip, [r0, #0]
ldr lr, [r0, #0]
subs r2, r2, #4
stmia r1!, {r3, r4, ip, lr}
bpl 1000b
ldmfd sp!, {r4, lr}
1001: tst r2, #2
ldrne r3, [r0, #0]
ldrne ip, [r0, #0]
stmneia r1!, {r3, ip}
tst r2, #1
ldrne r3, [r0, #0]
strne r3, [r1, #0]
mov pc, lr
2: cmp ip, #2
ldr ip, [r0]
blt 4f
bgt 6f
#ifndef __ARMEB__
/* little endian code */
strh ip, [r1], #2
mov ip, ip, lsr #16
3: subs r2, r2, #1
ldrne r3, [r0]
orrne ip, ip, r3, lsl #16
strne ip, [r1], #4
movne ip, r3, lsr #16
bne 3b
strh ip, [r1], #2
mov pc, lr
4: strb ip, [r1], #1
mov ip, ip, lsr #8
strh ip, [r1], #2
mov ip, ip, lsr #16
5: subs r2, r2, #1
ldrne r3, [r0]
orrne ip, ip, r3, lsl #8
strne ip, [r1], #4
movne ip, r3, lsr #24
bne 5b
strb ip, [r1], #1
mov pc, lr
6: strb ip, [r1], #1
mov ip, ip, lsr #8
7: subs r2, r2, #1
ldrne r3, [r0]
orrne ip, ip, r3, lsl #24
strne ip, [r1], #4
movne ip, r3, lsr #8
bne 7b
strh ip, [r1], #2
mov ip, ip, lsr #16
strb ip, [r1]
mov pc, lr
#else
/* big endian code */
mov r3, ip, lsr #16
strh r3, [r1], #2
3: mov r3, ip, lsl #16
subs r2, r2, #1
ldrne ip, [r0]
orrne r3, r3, ip, lsr #16
strne r3, [r1], #4
bne 3b
strh ip, [r1], #2
mov pc, lr
4: mov r3, ip, lsr #24
strb r3, [r1], #1
mov r3, ip, lsr #8
strh r3, [r1], #2
5: mov r3, ip, lsl #24
subs r2, r2, #1
ldrne ip, [r0]
orrne r3, r3, ip, lsr #8
strne r3, [r1], #4
bne 5b
strb ip, [r1], #1
mov pc, lr
6: mov r3, ip, lsr #24
strb r3, [r1], #1
7: mov r3, ip, lsl #8
subs r2, r2, #1
ldrne ip, [r0]
orrne r3, r3, ip, lsr #24
strne r3, [r1], #4
bne 7b
mov r3, ip, lsr #8
strh r3, [r1], #2
strb ip, [r1], #1
mov pc, lr
#endif
arch/arm/lib/io-readsl-armv3.S → arch/arm/lib/io-readsl.S
View file @ 010eeeac
/*
* linux/arch/arm/lib/io-readsl-armv3.S
* linux/arch/arm/lib/io-readsl.S
*
* Copyright (C) 1995-2000 Russell King
*
......@@ -9,70 +9,71 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/hardware.h>
/*
* Note that some reads can be aligned on half-word boundaries.
*/
ENTRY(__raw_readsl)
teq r2, #0 @ do we have to check for the zero len?
moveq pc, lr
ands ip, r1, #3
bne 2f
bne 3f
1: ldr r3, [r0]
str r3, [r1], #4
subs r2, r2, #1
bne 1b
subs r2, r2, #4
bmi 2f
stmfd sp!, {r4, lr}
1: ldr r3, [r0, #0]
ldr r4, [r0, #0]
ldr ip, [r0, #0]
ldr lr, [r0, #0]
subs r2, r2, #4
stmia r1!, {r3, r4, ip, lr}
bpl 1b
ldmfd sp!, {r4, lr}
2: tst r2, #2
ldrne r3, [r0, #0]
ldrne ip, [r0, #0]
stmneia r1!, {r3, ip}
tst r2, #1
ldrne r3, [r0, #0]
strne r3, [r1, #0]
mov pc, lr
2: cmp ip, #2
ldr ip, [r0]
blt 4f
3: ldr r3, [r0]
cmp ip, #2
mov ip, r3, get_byte_0
strb ip, [r1], #1
bgt 6f
mov ip, r3, get_byte_1
strb ip, [r1], #1
mov ip, ip, lsr #8
beq 5f
mov ip, r3, get_byte_2
strb ip, [r1], #1
mov ip, ip, lsr #8
3: subs r2, r2, #1
4: subs r2, r2, #1
mov ip, r3, pull #24
ldrne r3, [r0]
orrne ip, ip, r3, lsl #16
orrne ip, ip, r3, push #8
strne ip, [r1], #4
movne ip, r3, lsr #16
bne 3b
strb ip, [r1], #1
mov ip, ip, lsr #8
strb ip, [r1], #1
mov pc, lr
bne 4b
b 8f
4: strb ip, [r1], #1
mov ip, ip, lsr #8
strb ip, [r1], #1
mov ip, ip, lsr #8
strb ip, [r1], #1
mov ip, ip, lsr #8
5: subs r2, r2, #1
mov ip, r3, pull #16
ldrne r3, [r0]
orrne ip, ip, r3, lsl #8
orrne ip, ip, r3, push #16
strne ip, [r1], #4
movne ip, r3, lsr #24
bne 5b
strb ip, [r1], #1
mov pc, lr
b 7f
6: strb ip, [r1], #1
mov ip, ip, lsr #8
7: subs r2, r2, #1
6: subs r2, r2, #1
mov ip, r3, pull #8
ldrne r3, [r0]
orrne ip, ip, r3, lsl #24
orrne ip, ip, r3, push #24
strne ip, [r1], #4
movne ip, r3, lsr #8
bne 7b
strb ip, [r1], #1
mov ip, ip, lsr #8
strb ip, [r1], #1
mov ip, ip, lsr #8
strb ip, [r1], #1
mov pc, lr
bne 6b
mov r3, ip, get_byte_2
strb r3, [r1, #2]
7: mov r3, ip, get_byte_1
strb r3, [r1, #1]
8: mov r3, ip, get_byte_0
strb r3, [r1, #0]
mov pc, lr
arch/arm/lib/io-writesl.S
View file @ 010eeeac
......@@ -9,53 +9,59 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/hardware.h>
ENTRY(__raw_writesl)
teq r2, #0 @ do we have to check for the zero len?
moveq pc, lr
ands ip, r1, #3
bne 2f
bne 3f
subs r2, r2, #4
bmi 2f
stmfd sp!, {r4, lr}
1: ldmia r1!, {r3, r4, ip, lr}
subs r2, r2, #4
str r3, [r0, #0]
str r4, [r0, #0]
str ip, [r0, #0]
str lr, [r0, #0]
bpl 1b
ldmfd sp!, {r4, lr}
2: tst r2, #2
ldmneia r1!, {r3, ip}
strne r3, [r0, #0]
strne ip, [r0, #0]
tst r2, #1
ldrne r3, [r1], #4
ldrne r3, [r1, #0]
strne r3, [r0, #0]
1: subs r2, r2, #2
ldrcs r3, [r1], #4
ldrcs ip, [r1], #4
strcs r3, [r0, #0]
strcs ip, [r0, #0]
bcs 1b
mov pc, lr
2: bic r1, r1, #3
cmp ip, #2
3: bic r1, r1, #3
ldr r3, [r1], #4
bgt 4f
cmp ip, #2
blt 5f
bgt 6f
3: mov ip, r3, lsr #16
4: mov ip, r3, pull #16
ldr r3, [r1], #4
subs r2, r2, #1
orr ip, ip, r3, lsl #16
str ip, [r0, #0]
bne 3b
orr ip, ip, r3, push #16
str ip, [r0]
bne 4b
mov pc, lr
4: mov ip, r3, lsr #24
5: mov ip, r3, pull #8
ldr r3, [r1], #4
subs r2, r2, #1
orr ip, ip, r3, lsl #8
str ip, [r0, #0]
bne 4b
orr ip, ip, r3, push #24
str ip, [r0]
bne 5b
mov pc, lr
5: mov ip, r3, lsr #8
6: mov ip, r3, pull #24
ldr r3, [r1], #4
subs r2, r2, #1
orr ip, ip, r3, lsl #24
str ip, [r0, #0]
bne 5b
orr ip, ip, r3, push #8
str ip, [r0]
bne 6b
mov pc, lr
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