Commit 015cf329 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark

drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers

These drivers do not use vco_delay variable, so drop it from all of
them.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor
Link: https://lore.kernel.org/r/20210331105735.3690009-15-dmitry.baryshkov@linaro.orgSigned-off-by: default avatarRob Clark <robdclark@chromium.org>
parent aaadcbb4
...@@ -99,7 +99,6 @@ struct dsi_pll_10nm { ...@@ -99,7 +99,6 @@ struct dsi_pll_10nm {
/* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */ /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */
spinlock_t postdiv_lock; spinlock_t postdiv_lock;
int vco_delay;
struct dsi_pll_config pll_configuration; struct dsi_pll_config pll_configuration;
struct dsi_pll_regs reg_setup; struct dsi_pll_regs reg_setup;
...@@ -771,8 +770,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) ...@@ -771,8 +770,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
pll = &pll_10nm->base; pll = &pll_10nm->base;
pll->cfg = phy->cfg; pll->cfg = phy->cfg;
pll_10nm->vco_delay = 1;
ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws); ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
if (ret) { if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
......
...@@ -122,8 +122,6 @@ struct dsi_pll_14nm { ...@@ -122,8 +122,6 @@ struct dsi_pll_14nm {
void __iomem *phy_cmn_mmio; void __iomem *phy_cmn_mmio;
void __iomem *mmio; void __iomem *mmio;
int vco_delay;
struct dsi_pll_input in; struct dsi_pll_input in;
struct dsi_pll_output out; struct dsi_pll_output out;
...@@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) ...@@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
pll = &pll_14nm->base; pll = &pll_14nm->base;
pll->cfg = phy->cfg; pll->cfg = phy->cfg;
pll_14nm->vco_delay = 1;
ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws); ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
if (ret) { if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
......
...@@ -99,7 +99,6 @@ struct dsi_pll_7nm { ...@@ -99,7 +99,6 @@ struct dsi_pll_7nm {
/* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
spinlock_t postdiv_lock; spinlock_t postdiv_lock;
int vco_delay;
struct dsi_pll_config pll_configuration; struct dsi_pll_config pll_configuration;
struct dsi_pll_regs reg_setup; struct dsi_pll_regs reg_setup;
...@@ -796,8 +795,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) ...@@ -796,8 +795,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
pll = &pll_7nm->base; pll = &pll_7nm->base;
pll->cfg = phy->cfg; pll->cfg = phy->cfg;
pll_7nm->vco_delay = 1;
ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws); ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
if (ret) { if (ret) {
DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
......
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