Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk

into ppc970.osdl.org:/home/torvalds/v2.6/linux

arch/arm/boot/compressed/ofw-shark.c

@@ -24,6 +24,8 @@ create_params (unsigned long *buffer)
 	int j,i,m,k,nr_banks,size;
 	unsigned char *c;
 
+	k = 0;
+
 	/* Head of the taglist */
 	tag->hdr.tag  = ATAG_CORE;
 	tag->hdr.size = tag_size(tag_core);

arch/arm/common/via82c505.c

@@ -59,7 +59,7 @@ static struct pci_ops via82c505_ops = {
 	.write	= via82c505_write_config,
 };
 
-void __init via82c505_preinit(void *sysdata)
+void __init via82c505_preinit(void)
 {
 	printk(KERN_DEBUG "PCI: VIA 82c505\n");
 	if (!request_region(0xA8,2,"via config")) {

arch/arm/kernel/entry-armv.S

@@ -379,8 +379,6 @@ __und_usr:
 	.previous
 
 /*
- * r0 = instruction.
- *
  * Check whether the instruction is a co-processor instruction.
  * If yes, we need to call the relevant co-processor handler.
  *
@@ -391,8 +389,9 @@ __und_usr:
  * for the ARM6/ARM7 SWI bug.
  *
  * Emulators may wish to make use of the following registers:
- *  r0  - instruction opcode.
- *  r10 - this threads thread_info structure.
+ *  r0  = instruction opcode.
+ *  r2  = PC+4
+ *  r10 = this threads thread_info structure.
  */
 call_fpe:
 	tst	r0, #0x08000000			@ only CDP/CPRT/LDC/STC have bit 27
@@ -447,7 +446,7 @@ do_fpe:
 /*
  * The FP module is called with these registers set:
  *  r0  = instruction
- *  r5  = PC
+ *  r2  = PC+4
  *  r9  = normal "successful" return address
  *  r10 = FP workspace
  *  lr  = unrecognised FP instruction return address

arch/arm/mach-h720x/Kconfig

@@ -27,5 +27,12 @@ config CPU_H7202
 	bool
 	help
 	  Select code specific to h7202 variants
+config H7202_SERIAL23
+	depends on CPU_H7202
+	bool "Use serial ports 2+3"
+	help
+	  Say Y here if you wish to use serial ports 2+3. They share their
+	  pins with the keyboard matrix controller, so you have to decide.
+
 
 endif

arch/arm/mach-h720x/cpu-h7202.c

@@ -5,7 +5,7 @@
  *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
  *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
  *
- * processor specific stuff for the Hynix h7201
+ * processor specific stuff for the Hynix h7202
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -48,7 +48,8 @@ static struct platform_device h7202ps2_device = {
 
 static struct plat_serial8250_port serial_platform_data[] = {
 	{
-		.membase	= SERIAL0_BASE,
+		.membase	= (void*)SERIAL0_VIRT,
+		.mapbase	= SERIAL0_BASE,
 		.irq		= IRQ_UART0,
 		.uartclk	= 2*1843200,
 		.regshift	= 2,
@@ -56,15 +57,18 @@ static struct plat_serial8250_port serial_platform_data[] = {
 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 	},
 	{
-		.membase	= SERIAL1_BASE,
+		.membase	= (void*)SERIAL1_VIRT,
+		.mapbase	= SERIAL1_BASE,
 		.irq		= IRQ_UART1,
 		.uartclk	= 2*1843200,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 	},
+#ifdef CONFIG_H7202_SERIAL23
 	{
-		.membase	= SERIAL2_BASE,
+		.membase	= (void*)SERIAL2_VIRT,
+		.mapbase	= SERIAL2_BASE,
 		.irq		= IRQ_UART2,
 		.uartclk	= 2*1843200,
 		.regshift	= 2,
@@ -72,13 +76,15 @@ static struct plat_serial8250_port serial_platform_data[] = {
 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 	},
 	{
-		.membase	= SERIAL3_BASE,
+		.membase	= (void*)SERIAL3_VIRT,
+		.mapbase	= SERIAL3_BASE,
 		.irq		= IRQ_UART3,
 		.uartclk	= 2*1843200,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 	},
+#endif
 	{ },
 };
 
@@ -210,5 +216,13 @@ void __init init_hw_h7202(void)
 	/* Enable clocks */
 	CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
 
+	CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
+	CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
+#ifdef CONFIG_H7202_SERIAL23
+	CPU_REG (SERIAL2_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
+	CPU_REG (SERIAL3_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
+	CPU_IO (GPIO_AMULSEL) = AMULSEL_USIN2 | AMULSEL_USOUT2 |
+	                        AMULSEL_USIN3 | AMULSEL_USOUT3;
+#endif
 	(void) platform_add_devices(devices, ARRAY_SIZE(devices));
 }

arch/arm/mach-shark/core.c

@@ -93,8 +93,6 @@ static struct irqaction shark_timer_irq = {
  */
 static void __init shark_timer_init(void)
 {
-        unsigned long flags;
-
 	outb(0x34, 0x43);               /* binary, mode 0, LSB/MSB, Ch 0 */
 	outb(HZ_TIME & 0xff, 0x40);     /* LSB of count */
 	outb(HZ_TIME >> 8, 0x40);

arch/arm/mach-shark/irq.c

@@ -61,9 +61,10 @@ static void shark_enable_8259A_irq(unsigned int irq)
 
 static void shark_ack_8259A_irq(unsigned int irq){}
 
-static void bogus_int(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t bogus_int(int irq, void *dev_id, struct pt_regs *regs)
 {
 	printk("Got interrupt %i!\n",irq);
+	return IRQ_NONE;
 }
 
 static struct irqaction cascade;
@@ -103,7 +104,6 @@ void __init shark_init_irq(void)
 
 	cascade.handler = bogus_int;
 	cascade.flags = 0;
-	cascade.mask = 0;
 	cascade.name = "cascade";
 	cascade.next = NULL;
 	cascade.dev_id = NULL;

arch/arm/mach-shark/pci.c

@@ -21,7 +21,7 @@ static int __init shark_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 	else return 255;
 }
 
-extern void __init via82c505_preinit(void *sysdata);
+extern void __init via82c505_preinit(void);
 
 static struct hw_pci shark_pci __initdata = {
 	.setup		= via82c505_setup,
@@ -29,7 +29,7 @@ static struct hw_pci shark_pci __initdata = {
 	.map_irq	= shark_map_irq,
 	.nr_controllers = 1,
 	.scan		= via82c505_scan_bus,
-	.preinit	= via82c505_preinit
+	.preinit	= via82c505_preinit,
 };
 
 static int __init shark_pci_init(void)

arch/arm/vfp/vfphw.S

@@ -62,14 +62,14 @@
 @ VFP hardware support entry point.
 @
 @  r0  = faulted instruction
-@  r5  = faulted PC+4
+@  r2  = faulted PC+4
 @  r9  = successful return
 @  r10 = vfp_state union
 @  lr  = failure return
 
 	.globl	vfp_support_entry
 vfp_support_entry:
-	DBGSTR3	"instr %08x pc %08x state %p", r0, r5, r10
+	DBGSTR3	"instr %08x pc %08x state %p", r0, r2, r10
 
 	VFPFMRX	r1, FPEXC		@ Is the VFP enabled?
 	DBGSTR1	"fpexc %08x", r1
@@ -80,14 +80,14 @@ vfp_support_entry:
 	ldr	r3, last_VFP_context_address
 	orr	r1, r1, #FPEXC_ENABLE	@ user FPEXC has the enable bit set
 	ldr	r4, [r3]		@ last_VFP_context pointer
-	bic	r2, r1, #FPEXC_EXCEPTION @ make sure exceptions are disabled
+	bic	r5, r1, #FPEXC_EXCEPTION @ make sure exceptions are disabled
 	cmp	r4, r10
 	beq	check_for_exception	@ we are returning to the same
 					@ process, so the registers are
 					@ still there.  In this case, we do
 					@ not want to drop a pending exception.
 
-	VFPFMXR	FPEXC, r2		@ enable VFP, disable any pending
+	VFPFMXR	FPEXC, r5		@ enable VFP, disable any pending
 					@ exceptions, so we can get at the
 					@ rest of it
 
@@ -96,14 +96,14 @@ vfp_support_entry:
 	DBGSTR1	"save old state %p", r4
 	cmp	r4, #0
 	beq	no_old_VFP_process
-	VFPFMRX	r2, FPSCR		@ current status
+	VFPFMRX	r5, FPSCR		@ current status
 	VFPFMRX	r6, FPINST		@ FPINST (always there, rev0 onwards)
 	tst	r1, #FPEXC_FPV2		@ is there an FPINST2 to read?
 	VFPFMRX	r8, FPINST2, NE		@ FPINST2 if needed - avoids reading
 					@ nonexistant reg on rev0
 	VFPFSTMIA r4 			@ save the working registers
 	add	r4, r4, #8*16+4
-	stmia	r4, {r1, r2, r6, r8}	@ save FPEXC, FPSCR, FPINST, FPINST2
+	stmia	r4, {r1, r5, r6, r8}	@ save FPEXC, FPSCR, FPINST, FPINST2
 					@ and point r4 at the word at the
 					@ start of the register dump
 
@@ -112,14 +112,14 @@ no_old_VFP_process:
 	str	r10, [r3]		@ update the last_VFP_context pointer
 					@ Load the saved state back into the VFP
 	add	r4, r10, #8*16+4
-	ldmia	r4, {r1, r2, r6, r8}	@ load FPEXC, FPSCR, FPINST, FPINST2
+	ldmia	r4, {r1, r5, r6, r8}	@ load FPEXC, FPSCR, FPINST, FPINST2
 	VFPFLDMIA r10	 		@ reload the working registers while
 					@ FPEXC is in a safe state
 	tst	r1, #FPEXC_FPV2		@ is there an FPINST2 to write?
 	VFPFMXR	FPINST2, r8, NE		@ FPINST2 if needed - avoids writing
 					@ nonexistant reg on rev0
 	VFPFMXR	FPINST, r6
-	VFPFMXR	FPSCR, r2		@ restore status
+	VFPFMXR	FPSCR, r5		@ restore status
 
 check_for_exception:
 	tst	r1, #FPEXC_EXCEPTION
@@ -128,16 +128,16 @@ check_for_exception:
 					@ out before setting an FPEXC that
 					@ stops us reading stuff
 	VFPFMXR	FPEXC, r1		@ restore FPEXC last
-	sub	r5, r5, #4
-	str	r5, [sp, #S_PC]		@ retry the instruction
+	sub	r2, r2, #4
+	str	r2, [sp, #S_PC]		@ retry the instruction
 	mov	pc, r9			@ we think we have handled things
 
 
 look_for_VFP_exceptions:
 	tst	r1, #FPEXC_EXCEPTION
 	bne	process_exception
-	VFPFMRX	r2, FPSCR
-	tst	r2, #FPSCR_IXE		@ IXE doesn't set FPEXC_EXCEPTION !
+	VFPFMRX	r5, FPSCR
+	tst	r5, #FPSCR_IXE		@ IXE doesn't set FPEXC_EXCEPTION !
 	bne	process_exception
 
 	@ Fall into hand on to next handler - appropriate coproc instr
@@ -148,8 +148,8 @@ look_for_VFP_exceptions:
 
 process_exception:
 	DBGSTR	"bounce"
-	sub	r5, r5, #4
-	str	r5, [sp, #S_PC]		@ retry the instruction on exit from
+	sub	r2, r2, #4
+	str	r2, [sp, #S_PC]		@ retry the instruction on exit from
 					@ the imprecise exception handling in
 					@ the support code
 	mov	r2, sp			@ nothing stacked - regdump is at TOS

include/asm-arm/arch-h720x/h7202-regs.h

@@ -17,8 +17,12 @@
  * which is included by this file.
  */
 
-#define SERIAL2_VIRT 		(IO_VIRT + 0x2d000)
-#define SERIAL3_VIRT 		(IO_VIRT + 0x2e000)
+#define SERIAL2_OFS		0x2d000
+#define SERIAL2_BASE		(IO_PHYS + SERIAL2_OFS)
+#define SERIAL2_VIRT 		(IO_VIRT + SERIAL2_OFS)
+#define SERIAL3_OFS		0x2e000
+#define SERIAL3_BASE		(IO_PHYS + SERIAL3_OFS)
+#define SERIAL3_VIRT 		(IO_VIRT + SERIAL3_OFS)
 
 /* Matrix Keyboard Controller */
 #define KBD_VIRT		(IO_VIRT + 0x22000)

include/asm-arm/arch-h720x/hardware.h

@@ -52,7 +52,15 @@
 #define GPIO_C_VIRT		(GPIO_VIRT(2))
 #define GPIO_D_VIRT		(GPIO_VIRT(3))
 #define GPIO_E_VIRT		(GPIO_VIRT(4))
-#define GPIO_AMULSEL		(GPIO_VIRT + 0xA4)
+#define GPIO_AMULSEL		(GPIO_VIRT(0) + 0xA4)
+
+#define AMULSEL_USIN2	(1<<5)
+#define AMULSEL_USOUT2	(1<<6)
+#define AMULSEL_USIN3	(1<<13)
+#define AMULSEL_USOUT3	(1<<14)
+#define AMULSEL_IRDIN	(1<<15)
+#define AMULSEL_IRDOUT	(1<<7)
+
 /* Register offsets general purpose I/O */
 #define GPIO_DATA		0x00
 #define GPIO_DIR		0x04
@@ -162,14 +170,16 @@
 #define LCD_PALETTE_BASE 	(IO_VIRT + 0x10400)
 
 /* Serial ports */
-#define SERIAL0_VIRT 		(IO_VIRT + 0x20000)
-#define SERIAL1_VIRT 		(IO_VIRT + 0x21000)
+#define SERIAL0_OFS		0x20000
+#define SERIAL0_VIRT 		(IO_VIRT + SERIAL0_OFS)
+#define SERIAL0_BASE		(IO_PHYS + SERIAL0_OFS)
 
-#define SERIAL0_BASE		SERIAL0_VIRT
-#define SERIAL1_BASE		SERIAL1_VIRT
-#define SERIAL2_BASE		SERIAL2_VIRT
-#define SERIAL3_BASE		SERIAL3_VIRT
+#define SERIAL1_OFS		0x21000
+#define SERIAL1_VIRT 		(IO_VIRT + SERIAL1_OFS)
+#define SERIAL1_BASE		(IO_PHYS + SERIAL1_OFS)
 
+#define SERIAL_ENABLE		0x30
+#define SERIAL_ENABLE_EN	(1<<0)
 
 /* General defines to pacify gcc */
 #define PCIO_BASE 		(0)	/* for inb, outb and friends */

include/asm-arm/arch-ixp2000/io.h

@@ -21,14 +21,14 @@
 /*
  * Pick up VMALLOC_END
  */
-#define ___io(p)		((unsigned long)((p)+IXP2000_PCI_IO_VIRT_BASE))
+#define ___io(p)		((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
 
 /*
  * IXP2000 does not do proper byte-lane conversion for PCI addresses,
  * so we need to override standard functions.
  */
-#define alignb(addr)		((addr & ~3) + (3 - (addr & 3)))
-#define alignw(addr)		((addr & ~2) + (2 - (addr & 2)))
+#define alignb(addr)		(((unsigned long)addr & ~3) + (3 - ((unsigned long)addr & 3)))
+#define alignw(addr)		(((unsigned long)addr & ~2) + (2 - ((unsigned long)addr & 2)))
 
 #define outb(v,p)		__raw_writeb(v,alignb(___io(p)))
 #define outw(v,p)		__raw_writew((v),alignw(___io(p)))