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Commit 02dc14d6 authored by Mark Brown's avatar Mark Brown
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Merge remote-tracking branches 'asoc/topic/wm8741', 'asoc/topic/wm8753',... 

Merge remote-tracking branches 'asoc/topic/wm8741', 'asoc/topic/wm8753', 'asoc/topic/wm8904', 'asoc/topic/wm8960' and 'asoc/topic/wm8983' into asoc-next
parents 384ea793 84eac619 b9704998 779ea473 3176bf2d 85e71184
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Showing with 211 additions and 162 deletions
sound/soc/codecs/wm8741.c
View file @ 02dc14d6
......@@ -61,25 +61,6 @@ static const struct reg_default wm8741_reg_defaults[] = {
{ 32, 0x0002 }, /* R32 - ADDITONAL_CONTROL_1 */
};
static bool wm8741_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
case WM8741_DACLLSB_ATTENUATION:
case WM8741_DACLMSB_ATTENUATION:
case WM8741_DACRLSB_ATTENUATION:
case WM8741_DACRMSB_ATTENUATION:
case WM8741_VOLUME_CONTROL:
case WM8741_FORMAT_CONTROL:
case WM8741_FILTER_CONTROL:
case WM8741_MODE_CONTROL_1:
case WM8741_MODE_CONTROL_2:
case WM8741_ADDITIONAL_CONTROL_1:
return true;
default:
return false;
}
}
static int wm8741_reset(struct snd_soc_codec *codec)
{
return snd_soc_write(codec, WM8741_RESET, 0);
......@@ -278,51 +259,38 @@ static int wm8741_set_dai_sysclk(struct snd_soc_dai *codec_dai,
switch (freq) {
case 0:
wm8741->sysclk_constraints = NULL;
wm8741->sysclk = freq;
return 0;
break;
case 11289600:
wm8741->sysclk_constraints = &constraints_11289;
wm8741->sysclk = freq;
return 0;
break;
case 12288000:
wm8741->sysclk_constraints = &constraints_12288;
wm8741->sysclk = freq;
return 0;
break;
case 16384000:
wm8741->sysclk_constraints = &constraints_16384;
wm8741->sysclk = freq;
return 0;
break;
case 16934400:
wm8741->sysclk_constraints = &constraints_16934;
wm8741->sysclk = freq;
return 0;
break;
case 18432000:
wm8741->sysclk_constraints = &constraints_18432;
wm8741->sysclk = freq;
return 0;
break;
case 22579200:
case 33868800:
wm8741->sysclk_constraints = &constraints_22579;
wm8741->sysclk = freq;
return 0;
break;
case 24576000:
wm8741->sysclk_constraints = &constraints_24576;
wm8741->sysclk = freq;
return 0;
break;
case 36864000:
wm8741->sysclk_constraints = &constraints_36864;
wm8741->sysclk = freq;
return 0;
break;
default:
return -EINVAL;
}
return -EINVAL;
wm8741->sysclk = freq;
return 0;
}
static int wm8741_set_dai_fmt(struct snd_soc_dai *codec_dai,
......@@ -554,8 +522,6 @@ static const struct regmap_config wm8741_regmap = {
.reg_defaults = wm8741_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8741_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.readable_reg = wm8741_readable,
};
static int wm8741_set_pdata(struct device *dev, struct wm8741_priv *wm8741)
......
sound/soc/codecs/wm8753.c
View file @ 02dc14d6
......@@ -138,11 +138,6 @@ static bool wm8753_volatile(struct device *dev, unsigned int reg)
return reg == WM8753_RESET;
}
static bool wm8753_writeable(struct device *dev, unsigned int reg)
{
return reg <= WM8753_ADCTL2;
}
/* codec private data */
struct wm8753_priv {
struct regmap *regmap;
......@@ -1509,7 +1504,6 @@ static const struct regmap_config wm8753_regmap = {
.val_bits = 9,
.max_register = WM8753_ADCTL2,
.writeable_reg = wm8753_writeable,
.volatile_reg = wm8753_volatile,
.cache_type = REGCACHE_RBTREE,
......
sound/soc/codecs/wm8904.c
View file @ 02dc14d6
......@@ -1837,7 +1837,9 @@ static int wm8904_set_bias_level(struct snd_soc_codec *codec,
switch (level) {
case SND_SOC_BIAS_ON:
clk_prepare_enable(wm8904->mclk);
ret = clk_prepare_enable(wm8904->mclk);
if (ret)
return ret;
break;
case SND_SOC_BIAS_PREPARE:
......
sound/soc/codecs/wm8960.c
View file @ 02dc14d6
This diff is collapsed.
sound/soc/codecs/wm8960.h
View file @ 02dc14d6
......@@ -82,6 +82,7 @@
#define WM8960_SYSCLK_MCLK (0 << 0)
#define WM8960_SYSCLK_PLL (1 << 0)
#define WM8960_SYSCLK_AUTO (2 << 0)
#define WM8960_DAC_DIV_1 (0 << 3)
#define WM8960_DAC_DIV_1_5 (1 << 3)
......
sound/soc/codecs/wm8983.c
View file @ 02dc14d6
......@@ -84,66 +84,6 @@ static const struct reg_default wm8983_defaults[] = {
{ 0x3D, 0x0000 }, /* R61 - BIAS CTRL */
};
static const struct wm8983_reg_access {
u16 read; /* Mask of readable bits */
u16 write; /* Mask of writable bits */
} wm8983_access_masks[WM8983_MAX_REGISTER + 1] = {
[0x00] = { 0x0000, 0x01FF }, /* R0 - Software Reset */
[0x01] = { 0x0000, 0x01FF }, /* R1 - Power management 1 */
[0x02] = { 0x0000, 0x01FF }, /* R2 - Power management 2 */
[0x03] = { 0x0000, 0x01EF }, /* R3 - Power management 3 */
[0x04] = { 0x0000, 0x01FF }, /* R4 - Audio Interface */
[0x05] = { 0x0000, 0x003F }, /* R5 - Companding control */
[0x06] = { 0x0000, 0x01FD }, /* R6 - Clock Gen control */
[0x07] = { 0x0000, 0x000F }, /* R7 - Additional control */
[0x08] = { 0x0000, 0x003F }, /* R8 - GPIO Control */
[0x09] = { 0x0000, 0x0070 }, /* R9 - Jack Detect Control 1 */
[0x0A] = { 0x0000, 0x004F }, /* R10 - DAC Control */
[0x0B] = { 0x0000, 0x01FF }, /* R11 - Left DAC digital Vol */
[0x0C] = { 0x0000, 0x01FF }, /* R12 - Right DAC digital vol */
[0x0D] = { 0x0000, 0x00FF }, /* R13 - Jack Detect Control 2 */
[0x0E] = { 0x0000, 0x01FB }, /* R14 - ADC Control */
[0x0F] = { 0x0000, 0x01FF }, /* R15 - Left ADC Digital Vol */
[0x10] = { 0x0000, 0x01FF }, /* R16 - Right ADC Digital Vol */
[0x12] = { 0x0000, 0x017F }, /* R18 - EQ1 - low shelf */
[0x13] = { 0x0000, 0x017F }, /* R19 - EQ2 - peak 1 */
[0x14] = { 0x0000, 0x017F }, /* R20 - EQ3 - peak 2 */
[0x15] = { 0x0000, 0x017F }, /* R21 - EQ4 - peak 3 */
[0x16] = { 0x0000, 0x007F }, /* R22 - EQ5 - high shelf */
[0x18] = { 0x0000, 0x01FF }, /* R24 - DAC Limiter 1 */
[0x19] = { 0x0000, 0x007F }, /* R25 - DAC Limiter 2 */
[0x1B] = { 0x0000, 0x01FF }, /* R27 - Notch Filter 1 */
[0x1C] = { 0x0000, 0x017F }, /* R28 - Notch Filter 2 */
[0x1D] = { 0x0000, 0x017F }, /* R29 - Notch Filter 3 */
[0x1E] = { 0x0000, 0x017F }, /* R30 - Notch Filter 4 */
[0x20] = { 0x0000, 0x01BF }, /* R32 - ALC control 1 */
[0x21] = { 0x0000, 0x00FF }, /* R33 - ALC control 2 */
[0x22] = { 0x0000, 0x01FF }, /* R34 - ALC control 3 */
[0x23] = { 0x0000, 0x000F }, /* R35 - Noise Gate */
[0x24] = { 0x0000, 0x001F }, /* R36 - PLL N */
[0x25] = { 0x0000, 0x003F }, /* R37 - PLL K 1 */
[0x26] = { 0x0000, 0x01FF }, /* R38 - PLL K 2 */
[0x27] = { 0x0000, 0x01FF }, /* R39 - PLL K 3 */
[0x29] = { 0x0000, 0x000F }, /* R41 - 3D control */
[0x2A] = { 0x0000, 0x01E7 }, /* R42 - OUT4 to ADC */
[0x2B] = { 0x0000, 0x01BF }, /* R43 - Beep control */
[0x2C] = { 0x0000, 0x0177 }, /* R44 - Input ctrl */
[0x2D] = { 0x0000, 0x01FF }, /* R45 - Left INP PGA gain ctrl */
[0x2E] = { 0x0000, 0x01FF }, /* R46 - Right INP PGA gain ctrl */
[0x2F] = { 0x0000, 0x0177 }, /* R47 - Left ADC BOOST ctrl */
[0x30] = { 0x0000, 0x0177 }, /* R48 - Right ADC BOOST ctrl */
[0x31] = { 0x0000, 0x007F }, /* R49 - Output ctrl */
[0x32] = { 0x0000, 0x01FF }, /* R50 - Left mixer ctrl */
[0x33] = { 0x0000, 0x01FF }, /* R51 - Right mixer ctrl */
[0x34] = { 0x0000, 0x01FF }, /* R52 - LOUT1 (HP) volume ctrl */
[0x35] = { 0x0000, 0x01FF }, /* R53 - ROUT1 (HP) volume ctrl */
[0x36] = { 0x0000, 0x01FF }, /* R54 - LOUT2 (SPK) volume ctrl */
[0x37] = { 0x0000, 0x01FF }, /* R55 - ROUT2 (SPK) volume ctrl */
[0x38] = { 0x0000, 0x004F }, /* R56 - OUT3 mixer ctrl */
[0x39] = { 0x0000, 0x00FF }, /* R57 - OUT4 (MONO) mix ctrl */
[0x3D] = { 0x0000, 0x0100 } /* R61 - BIAS CTRL */
};
/* vol/gain update regs */
static const int vol_update_regs[] = {
WM8983_LEFT_DAC_DIGITAL_VOL,
......@@ -605,12 +545,19 @@ static int eqmode_put(struct snd_kcontrol *kcontrol,
return 0;
}
static bool wm8983_readable(struct device *dev, unsigned int reg)
static bool wm8983_writeable(struct device *dev, unsigned int reg)
{
if (reg > WM8983_MAX_REGISTER)
return 0;
return wm8983_access_masks[reg].read != 0;
switch (reg) {
case WM8983_SOFTWARE_RESET ... WM8983_RIGHT_ADC_DIGITAL_VOL:
case WM8983_EQ1_LOW_SHELF ... WM8983_DAC_LIMITER_2:
case WM8983_NOTCH_FILTER_1 ... WM8983_NOTCH_FILTER_4:
case WM8983_ALC_CONTROL_1 ... WM8983_PLL_K_3:
case WM8983_3D_CONTROL ... WM8983_OUT4_MONO_MIX_CTRL:
case WM8983_BIAS_CTRL:
return true;
default:
return false;
}
}
static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute)
......@@ -1048,8 +995,9 @@ static const struct regmap_config wm8983_regmap = {
.reg_defaults = wm8983_defaults,
.num_reg_defaults = ARRAY_SIZE(wm8983_defaults),
.cache_type = REGCACHE_RBTREE,
.max_register = WM8983_MAX_REGISTER,
.readable_reg = wm8983_readable,
.writeable_reg = wm8983_writeable,
};
#if defined(CONFIG_SPI_MASTER)
......
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