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Commit 02e2af20 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 

Pull char/misc and other driver updates from Greg KH:
 "Here is the big set of char/misc and other small driver subsystem
  updates for 5.18-rc1.

  Included in here are merges from driver subsystems which contain:

   - iio driver updates and new drivers

   - fsi driver updates

   - fpga driver updates

   - habanalabs driver updates and support for new hardware

   - soundwire driver updates and new drivers

   - phy driver updates and new drivers

   - coresight driver updates

   - icc driver updates

  Individual changes include:

   - mei driver updates

   - interconnect driver updates

   - new PECI driver subsystem added

   - vmci driver updates

   - lots of tiny misc/char driver updates

  All of these have been in linux-next for a while with no reported
  problems"

* tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (556 commits)
  firmware: google: Properly state IOMEM dependency
  kgdbts: fix return value of __setup handler
  firmware: sysfb: fix platform-device leak in error path
  firmware: stratix10-svc: add missing callback parameter on RSU
  arm64: dts: qcom: add non-secure domain property to fastrpc nodes
  misc: fastrpc: Add dma handle implementation
  misc: fastrpc: Add fdlist implementation
  misc: fastrpc: Add helper function to get list and page
  misc: fastrpc: Add support to secure memory map
  dt-bindings: misc: add fastrpc domain vmid property
  misc: fastrpc: check before loading process to the DSP
  misc: fastrpc: add secure domain support
  dt-bindings: misc: add property to support non-secure DSP
  misc: fastrpc: Add support to get DSP capabilities
  misc: fastrpc: add support for FASTRPC_IOCTL_MEM_MAP/UNMAP
  misc: fastrpc: separate fastrpc device from channel context
  dt-bindings: nvmem: brcm,nvram: add basic NVMEM cells
  dt-bindings: nvmem: make "reg" property optional
  nvmem: brcm_nvram: parse NVRAM content into NVMEM cells
  nvmem: dt-bindings: Fix the error of dt-bindings check
  ...
parents ff61bc81 37fd8391
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View file @ 02e2af20
......@@ -71,6 +71,7 @@ Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
Brian Avery <b.avery@hp.com>
Brian King <brking@us.ibm.com>
Brian Silverman <bsilver16384@gmail.com> <brian.silverman@bluerivertech.com>
Cai Huoqing <cai.huoqing@linux.dev> <caihuoqing@baidu.com>
Changbin Du <changbin.du@intel.com> <changbin.du@gmail.com>
Changbin Du <changbin.du@intel.com> <changbin.du@intel.com>
Chao Yu <chao@kernel.org> <chao2.yu@samsung.com>
......
Documentation/ABI/stable/sysfs-driver-firmware-zynqmp
View file @ 02e2af20
......@@ -113,3 +113,144 @@ Description:
# echo 0 > /sys/devices/platform/firmware\:zynqmp-firmware/health_status
Users: Xilinx
What: /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
Date: Feb 2022
KernelVersion: 5.18
Contact: "Ronak Jain" <ronak.jain@xilinx.com>
Description:
This sysfs interface allows user to configure features at
runtime. The user can enable or disable features running at
firmware as well as the user can configure the parameters of
the features at runtime. The supported features are over
temperature and external watchdog. Here, the external watchdog
is completely different than the /dev/watchdog as the external
watchdog is running on the firmware and it is used to monitor
the health of firmware not APU(Linux). Also, the external
watchdog is interfaced outside of the zynqmp soc.
The supported config ids are for the feature configuration is,
1. PM_FEATURE_OVERTEMP_STATUS = 1, the user can enable or
disable the over temperature feature.
2. PM_FEATURE_OVERTEMP_VALUE = 2, the user can configure the
over temperature limit in Degree Celsius.
3. PM_FEATURE_EXTWDT_STATUS = 3, the user can enable or disable
the external watchdog feature.
4. PM_FEATURE_EXTWDT_VALUE = 4, the user can configure the
external watchdog feature.
Usage:
Select over temperature config ID to enable/disable feature
# echo 1 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
Check over temperature config ID is selected or not
# cat /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
The expected result is 1.
Select over temperature config ID to configure OT limit
# echo 2 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
Check over temperature config ID is selected or not
# cat /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
The expected result is 2.
Select external watchdog config ID to enable/disable feature
# echo 3 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
Check external watchdog config ID is selected or not
# cat /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
The expected result is 3.
Select external watchdog config ID to configure time interval
# echo 4 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
Check external watchdog config ID is selected or not
# cat /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
The expected result is 4.
Users: Xilinx
What: /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
Date: Feb 2022
KernelVersion: 5.18
Contact: "Ronak Jain" <ronak.jain@xilinx.com>
Description:
This sysfs interface allows to configure features at runtime.
The user can enable or disable features running at firmware.
Also, the user can configure the parameters of the features
at runtime. The supported features are over temperature and
external watchdog. Here, the external watchdog is completely
different than the /dev/watchdog as the external watchdog is
running on the firmware and it is used to monitor the health
of firmware not APU(Linux). Also, the external watchdog is
interfaced outside of the zynqmp soc.
By default the features are disabled in the firmware. The user
can enable features by querying appropriate config id of the
features.
The default limit for the over temperature is 90 Degree Celsius.
The default timer interval for the external watchdog is 570ms.
The supported config ids are for the feature configuration is,
1. PM_FEATURE_OVERTEMP_STATUS = 1, the user can enable or
disable the over temperature feature.
2. PM_FEATURE_OVERTEMP_VALUE = 2, the user can configure the
over temperature limit in Degree Celsius.
3. PM_FEATURE_EXTWDT_STATUS = 3, the user can enable or disable
the external watchdog feature.
4. PM_FEATURE_EXTWDT_VALUE = 4, the user can configure the
external watchdog feature.
Usage:
Enable over temperature feature
# echo 1 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
# echo 1 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
Check whether the over temperature feature is enabled or not
# cat /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
The expected result is 1.
Disable over temperature feature
# echo 1 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
# echo 0 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
Check whether the over temperature feature is disabled or not
# cat /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
The expected result is 0.
Configure over temperature limit to 50 Degree Celsius
# echo 2 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
# echo 50 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
Check whether the over temperature limit is configured or not
# cat /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
The expected result is 50.
Enable external watchdog feature
# echo 3 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
# echo 1 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
Check whether the external watchdog feature is enabled or not
# cat /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
The expected result is 1.
Disable external watchdog feature
# echo 3 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
# echo 0 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
Check whether the external watchdog feature is disabled or not
# cat /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
The expected result is 0.
Configure external watchdog timer interval to 500ms
# echo 4 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_id
# echo 500 > /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
Check whether the external watchdog timer interval is configured or not
# cat /sys/devices/platform/firmware\:zynqmp-firmware/feature_config_value
The expected result is 500.
Users: Xilinx
Documentation/ABI/testing/debugfs-driver-habanalabs
View file @ 02e2af20
......@@ -12,24 +12,7 @@ What: /sys/kernel/debug/habanalabs/hl<n>/clk_gate
Date: May 2020
KernelVersion: 5.8
Contact: ogabbay@kernel.org
Description: Allow the root user to disable/enable in runtime the clock
gating mechanism in Gaudi. Due to how Gaudi is built, the
clock gating needs to be disabled in order to access the
registers of the TPC and MME engines. This is sometimes needed
during debug by the user and hence the user needs this option.
The user can supply a bitmask value, each bit represents
a different engine to disable/enable its clock gating feature.
The bitmask is composed of 20 bits:
======= ============
0 - 7 DMA channels
8 - 11 MME engines
12 - 19 TPC engines
======= ============
The bit's location of a specific engine can be determined
using (1 << GAUDI_ENGINE_ID_*). GAUDI_ENGINE_ID_* values
are defined in uapi habanalabs.h file in enum gaudi_engine_id
Description: This setting is now deprecated as clock gating is handled solely by the f/w
What: /sys/kernel/debug/habanalabs/hl<n>/command_buffers
Date: Jan 2019
......@@ -239,6 +222,7 @@ KernelVersion: 5.6
Contact: ogabbay@kernel.org
Description: Sets the stop-on_error option for the device engines. Value of
"0" is for disable, otherwise enable.
Relevant only for GOYA and GAUDI.
What: /sys/kernel/debug/habanalabs/hl<n>/timeout_locked
Date: Sep 2021
......
Documentation/ABI/testing/sysfs-bus-iio
View file @ 02e2af20
......@@ -476,6 +476,7 @@ What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_i_calibscale
What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_q_calibscale
What: /sys/bus/iio/devices/iio:deviceX/in_voltage_i_calibscale
What: /sys/bus/iio/devices/iio:deviceX/in_voltage_q_calibscale
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage_calibscale
What: /sys/bus/iio/devices/iio:deviceX/in_voltage_calibscale
What: /sys/bus/iio/devices/iio:deviceX/in_accel_x_calibscale
What: /sys/bus/iio/devices/iio:deviceX/in_accel_y_calibscale
......@@ -1213,6 +1214,32 @@ Description:
number or direction is not specified, applies to all channels of
this type.
What: /sys/.../iio:deviceX/events/in_accel_mag_referenced_en
What: /sys/.../iio:deviceX/events/in_accel_mag_referenced_rising_en
What: /sys/.../iio:deviceX/events/in_accel_mag_referenced_falling_en
What: /sys/.../iio:deviceX/events/in_accel_y_mag_referenced_en
What: /sys/.../iio:deviceX/events/in_accel_y_mag_referenced_rising_en
What: /sys/.../iio:deviceX/events/in_accel_y_mag_referenced_falling_en
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Similar to in_accel_mag[_y][_rising|_falling]_en, but the event
value is relative to a reference magnitude. The reference magnitude
includes the graviational acceleration.
What: /sys/.../iio:deviceX/events/in_accel_mag_referenced_value
What: /sys/.../iio:deviceX/events/in_accel_mag_referenced_rising_value
What: /sys/.../iio:deviceX/events/in_accel_mag_referenced_falling_value
What: /sys/.../iio:deviceX/events/in_accel_y_mag_referenced_value
What: /sys/.../iio:deviceX/events/in_accel_y_mag_referenced_rising_value
What: /sys/.../iio:deviceX/events/in_accel_y_mag_referenced_falling_value
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
The value to which the reference magnitude of the channel is
compared. If the axis is not specified, it applies to all channels
of this type.
What: /sys/.../events/in_steps_change_en
KernelVersion: 4.0
Contact: linux-iio@vger.kernel.org
......@@ -1252,6 +1279,10 @@ Description:
Actually start the buffer capture up. Will start trigger
if first device and appropriate.
Note that it might be impossible to configure other attributes,
(e.g.: events, scale, sampling rate) if they impact the currently
active buffer capture session.
What: /sys/bus/iio/devices/iio:deviceX/bufferY
KernelVersion: 5.11
Contact: linux-iio@vger.kernel.org
......
Documentation/ABI/testing/sysfs-bus-iio-adc-ad7280a 0 → 100644
View file @ 02e2af20
What: /sys/bus/iio/devices/iio:deviceX/in_voltageY-voltageZ_balance_switch_en
KernelVersion: 5.14
Contact: linux-iio@vger.kernel.org
Description:
Used to enable an output for balancing cells for time
controlled via in_voltage_Y-voltageZ_balance_switch_timer.
What: /sys/bus/iio/devices/iio:deviceX/in_voltageY-voltageZ_balance_switch_timer
KernelVersion: 5.14
Contact: linux-iio@vger.kernel.org
Description:
Time in seconds for which balance switch will be turned on.
Multiple of 71.5 seconds.
Documentation/ABI/testing/sysfs-bus-iio-dac-ltc2688 0 → 100644
View file @ 02e2af20
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_en
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Dither enable. Write 1 to enable dither or 0 to disable it. This is useful
for changing the dither parameters. They way it should be done is:
- disable dither operation;
- change dither parameters (eg: frequency, phase...);
- enabled dither operation
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_raw
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
This raw, unscaled value refers to the dither signal amplitude.
The same scale as in out_voltageY_raw applies. However, the
offset might be different as it's always 0 for this attribute.
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_raw_available
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Available range for dither raw amplitude values.
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_offset
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Offset applied to out_voltageY_dither_raw. Read only attribute
always set to 0.
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_frequency
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Sets the dither signal frequency. Units are in Hz.
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_frequency_available
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Returns the available values for the dither frequency.
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_phase
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Sets the dither signal phase. Units are in Radians.
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_phase_available
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Returns the available values for the dither phase.
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_toggle_en
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Toggle enable. Write 1 to enable toggle or 0 to disable it. This is
useful when one wants to change the DAC output codes. The way it should
be done is:
- disable toggle operation;
- change out_voltageY_raw0 and out_voltageY_raw1;
- enable toggle operation.
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_raw0
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_raw1
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
It has the same meaning as out_voltageY_raw. This attribute is
specific to toggle enabled channels and refers to the DAC output
code in INPUT_A (_raw0) and INPUT_B (_raw1). The same scale and offset
as in out_voltageY_raw applies.
What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_symbol
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Performs a SW toggle. This attribute is specific to toggle
enabled channels and allows to toggle between out_voltageY_raw0
and out_voltageY_raw1 through software. Writing 0 will select
out_voltageY_raw0 while 1 selects out_voltageY_raw1.
Documentation/ABI/testing/sysfs-bus-iio-frequency-admv1014 0 → 100644
View file @ 02e2af20
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_i_calibscale_coarse
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Read/write value for the digital attenuator gain (IF_I) with coarse steps.
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_q_calibscale_coarse
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Read/write value for the digital attenuator gain (IF_Q) with coarse steps.
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_i_calibscale_fine
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Read/write value for the digital attenuator gain (IF_I) with fine steps.
What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0_q_calibscale_fine
KernelVersion: 5.18
Contact: linux-iio@vger.kernel.org
Description:
Read/write value for the digital attenuator gain (IF_Q) with fine steps.
Documentation/ABI/testing/sysfs-bus-iio-sx9324 0 → 100644
View file @ 02e2af20
What: /sys/bus/iio/devices/iio:deviceX/in_proximity<id>_setup
Date: November 2021
KernelVersion: 5.17
Contact: Gwendal Grignou <gwendal@chromium.org>
Description:
SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout
defines if the input is
+ not connected (HZ),
+ grounded (GD),
+ connected to an antenna where it can act as a base
(DS - data shield), or measured input (MI).
The sensor rotates measurement across 4 phases
(PH0, PH1, PH2, PH3), where the inputs are configured
and then measured.
By default, during the first phase, [PH0], CS0 is measured,
while CS1 and CS2 are used as shields.
`cat in_proximity0_setup` returns "MI,DS,DS".
[PH1], CS1 is measured, CS0 and CS2 are shield:
`cat in_proximity1_setup` returns "DS,MI,DS".
[PH2], CS2 is measured, CS0 and CS1 are shield:
`cat in_proximity1_setup` returns "DS,DS,MI".
[PH3], CS1 and CS2 are measured (combo mode):
`cat in_proximity1_setup` returns "DS,MI,MI".
Note, these are the chip default. Hardware layout will most
likely dictate different output. The entry is read-only.
Documentation/ABI/testing/sysfs-bus-peci 0 → 100644
View file @ 02e2af20
What: /sys/bus/peci/rescan
Date: July 2021
KernelVersion: 5.18
Contact: Iwona Winiarska <iwona.winiarska@intel.com>
Description:
Writing a non-zero value to this attribute will
initiate scan for PECI devices on all PECI controllers
in the system.
What: /sys/bus/peci/devices/<controller_id>-<device_addr>/remove
Date: July 2021
KernelVersion: 5.18
Contact: Iwona Winiarska <iwona.winiarska@intel.com>
Description:
Writing a non-zero value to this attribute will
remove the PECI device and any of its children.
Documentation/ABI/testing/sysfs-driver-habanalabs
View file @ 02e2af20
......@@ -69,6 +69,12 @@ KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Displays the device's version from the eFuse
What: /sys/class/habanalabs/hl<n>/fw_os_ver
Date: Dec 2021
KernelVersion: 5.18
Contact: ogabbay@kernel.org
Description: Version of the firmware OS running on the device's CPU
What: /sys/class/habanalabs/hl<n>/hard_reset
Date: Jan 2019
KernelVersion: 5.1
......@@ -115,7 +121,7 @@ What: /sys/class/habanalabs/hl<n>/infineon_ver
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Version of the Device's power supply F/W code
Description: Version of the Device's power supply F/W code. Relevant only to GOYA and GAUDI
What: /sys/class/habanalabs/hl<n>/max_power
Date: Jan 2019
......@@ -220,4 +226,10 @@ What: /sys/class/habanalabs/hl<n>/uboot_ver
Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Version of the u-boot running on the device's CPU
\ No newline at end of file
Description: Version of the u-boot running on the device's CPU
What: /sys/class/habanalabs/hl<n>/vrm_ver
Date: Jan 2022
KernelVersion: not yet upstreamed
Contact: ogabbay@kernel.org
Description: Version of the Device's Voltage Regulator Monitor F/W code. N/A to GOYA and GAUDI
Documentation/devicetree/bindings/gpio/delta,tn48m-gpio.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/delta,tn48m-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Delta Networks TN48M CPLD GPIO controller
maintainers:
- Robert Marko <robert.marko@sartura.hr>
description: |
This module is part of the Delta TN48M multi-function device. For more
details see ../mfd/delta,tn48m-cpld.yaml.
Delta TN48M has an onboard Lattice CPLD that is used as an GPIO expander.
It provides 12 pins in total, they are input-only or ouput-only type.
properties:
compatible:
enum:
- delta,tn48m-gpo
- delta,tn48m-gpi
reg:
maxItems: 1
"#gpio-cells":
const: 2
gpio-controller: true
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
additionalProperties: false
Documentation/devicetree/bindings/iio/accel/adi,adxl367.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/accel/adi,adxl367.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices ADXL367 3-Axis Digital Accelerometer
maintainers:
- Cosmin Tanislav <cosmin.tanislav@analog.com>
description: |
The ADXL367 is an ultralow power, 3-axis MEMS accelerometer.
The ADXL367 does not alias input signals by to achieve ultralow power
consumption, it samples the full bandwidth of the sensor at all
data rates. Measurement ranges of +-2g, +-4g, and +-8g are available,
with a resolution of 0.25mg/LSB on the +-2 g range.
In addition to its ultralow power consumption, the ADXL367
has many features to enable true system level power reduction.
It includes a deep multimode output FIFO, a built-in micropower
temperature sensor, and an internal ADC for synchronous conversion
of an additional analog input.
https://www.analog.com/en/products/adxl367.html
properties:
compatible:
enum:
- adi,adxl367
reg:
maxItems: 1
interrupts:
maxItems: 1
spi-max-frequency: true
vdd-supply: true
vddio-supply: true
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
accelerometer@53 {
compatible = "adi,adxl367";
reg = <0x53>;
interrupt-parent = <&gpio>;
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
};
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
accelerometer@0 {
compatible = "adi,adxl367";
reg = <0>;
spi-max-frequency = <1000000>;
interrupt-parent = <&gpio>;
interrupts = <25 IRQ_TYPE_EDGE_RISING>;
};
};
Documentation/devicetree/bindings/iio/adc/adi,ad7280a.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/adi,ad7280a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices AD7280a Lithium Ion Battery Monitoring System
maintainers:
- Michael Hennerich <michael.hennerich@analog.com>
- Jonathan Cameron <jic23@kernel.org>
description: |
Bindings for the Analog Devices AD7280a Battery Monitoring System.
Used in devices such as hybrid electric cars, battery backup and power tools.
Multiple chips can be daisy chained and accessed via a single SPI interface.
Data sheet found here:
https://www.analog.com/media/en/technical-documentation/data-sheets/AD7280A.pdf
properties:
compatible:
const: adi,ad7280a
reg:
maxItems: 1
interrupts:
description: IRQ line for the ADC
maxItems: 1
spi-max-frequency: true
adi,voltage-alert-last-chan:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Allows limiting of scope of which channels are considered for voltage
alerts, typically because not all are wired to anything. Only applies to
last device in the daisy chain.
default: 5
enum: [3, 4, 5]
adi,acquisition-time-ns:
description:
Additional time may be needed to charge the sampling capacitors depending
on external writing.
default: 400
enum: [400, 800, 1200, 1600]
adi,thermistor-termination:
type: boolean
description:
Enable the thermistor termination function.
required:
- compatible
- reg
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
adc@0 {
compatible = "adi,ad7280a";
reg = <0>;
spi-max-frequency = <700000>;
interrupt-parent = <&gpio>;
interrupts = <25 2>;
adi,thermistor-termination;
adi,acquisition-time-ns = <800>;
adi,voltage-alert-last-chan = <5>;
};
};
...
Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml
View file @ 02e2af20
......@@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: AT91 SAMA5D2 Analog to Digital Converter (ADC)
maintainers:
- Ludovic Desroches <ludovic.desroches@atmel.com>
- Eugen Hristev <eugen.hristev@microchip.com>
properties:
......@@ -72,7 +71,6 @@ required:
- atmel,min-sample-rate-hz
- atmel,max-sample-rate-hz
- atmel,startup-time-ms
- atmel,trigger-edge-type
examples:
- |
......
Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
View file @ 02e2af20
......@@ -34,6 +34,7 @@ properties:
- items:
- enum:
- mediatek,mt8183-auxadc
- mediatek,mt8186-auxadc
- mediatek,mt8195-auxadc
- mediatek,mt8516-auxadc
- const: mediatek,mt8173-auxadc
......
Documentation/devicetree/bindings/iio/adc/microchip,mcp3201.yaml
View file @ 02e2af20
......@@ -10,7 +10,7 @@ maintainers:
- Oskar Andero <oskar.andero@gmail.com>
description: |
Family of simple ADCs with an I2C inteface.
Family of simple ADCs with a SPI interface.
properties:
compatible:
......
Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml
View file @ 02e2af20
......@@ -51,7 +51,7 @@ examples:
#size-cells = <0>;
pmic_iadc: adc@3600 {
compatible = "qcom,spmi-iadc";
reg = <0x3600 0x100>;
reg = <0x3600>;
interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
qcom,external-resistor-micro-ohms = <10000>;
#io-channel-cells = <1>;
......
Documentation/devicetree/bindings/iio/adc/ti,palmas-gpadc.yaml
View file @ 02e2af20
......@@ -74,9 +74,9 @@ examples:
compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
adc {
compatible = "ti,palmas-gpadc";
interrupts = <18 0
16 0
17 0>;
interrupts = <18 0>,
<16 0>,
<17 0>;
#io-channel-cells = <1>;
ti,channel0-current-microamp = <5>;
ti,channel3-current-microamp = <10>;
......
Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml
View file @ 02e2af20
......@@ -92,6 +92,10 @@ properties:
description: AMS Controller register space
maxItems: 1
clocks:
items:
- description: AMS reference clock
ranges:
description:
Maps the child address space for PS and/or PL.
......@@ -181,12 +185,15 @@ properties:
required:
- compatible
- reg
- clocks
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
......@@ -196,6 +203,7 @@ examples:
interrupt-parent = <&gic>;
interrupts = <0 56 4>;
reg = <0x0 0xffa50000 0x0 0x800>;
clocks = <&zynqmp_clk AMS_REF>;
#address-cells = <1>;
#size-cells = <1>;
#io-channel-cells = <1>;
......
Documentation/devicetree/bindings/iio/afe/temperature-sense-rtd.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/afe/temperature-sense-rtd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Temperature Sense RTD
maintainers:
- Liam Beguin <liambeguin@gmail.com>
description: |
RTDs (Resistance Temperature Detectors) are a kind of temperature sensors
used to get a linear voltage to temperature reading within a give range
(usually 0 to 100 degrees Celsius).
When an io-channel measures the output voltage across an RTD such as a
PT1000, the interesting measurement is almost always the corresponding
temperature, not the voltage output. This binding describes such a circuit.
The general transfer function here is (using SI units)
V = R(T) * iexc
R(T) = r0 * (1 + alpha * T)
T = 1 / (alpha * r0 * iexc) * (V - r0 * iexc)
The following circuit matches what's in the examples section.
5V0
-----
|
+---+----+
| R 5k |
+---+----+
|
V 1mA
|
+---- Vout
|
+---+----+
| PT1000 |
+---+----+
|
-----
GND
properties:
compatible:
const: temperature-sense-rtd
io-channels:
maxItems: 1
description: |
Channel node of a voltage io-channel.
'#io-channel-cells':
const: 0
excitation-current-microamp:
description: The current fed through the RTD sensor.
alpha-ppm-per-celsius:
description: |
alpha can also be expressed in micro-ohms per ohm Celsius. It's a linear
approximation of the resistance versus temperature relationship
between 0 and 100 degrees Celsius.
alpha = (R_100 - R_0) / (100 * R_0)
Where, R_100 is the resistance of the sensor at 100 degrees Celsius, and
R_0 (or r-naught-ohms) is the resistance of the sensor at 0 degrees
Celsius.
Pure platinum has an alpha of 3925. Industry standards such as IEC60751
and ASTM E-1137 specify an alpha of 3850.
r-naught-ohms:
description: |
Resistance of the sensor at 0 degrees Celsius.
Common values are 100 for PT100, 500 for PT500, and 1000 for PT1000
additionalProperties: false
required:
- compatible
- io-channels
- excitation-current-microamp
- alpha-ppm-per-celsius
- r-naught-ohms
examples:
- |
pt1000_1: temperature-sensor0 {
compatible = "temperature-sense-rtd";
#io-channel-cells = <0>;
io-channels = <&temp_adc1 0>;
excitation-current-microamp = <1000>; /* i = U/R = 5 / 5000 */
alpha-ppm-per-celsius = <3908>;
r-naught-ohms = <1000>;
};
...
Documentation/devicetree/bindings/iio/afe/temperature-transducer.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/afe/temperature-transducer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Temperature Transducer
maintainers:
- Liam Beguin <liambeguin@gmail.com>
description: |
A temperature transducer is a device that converts a thermal quantity
into any other physical quantity. This binding applies to temperature to
voltage (like the LTC2997), and temperature to current (like the AD590)
linear transducers.
In both cases these are assumed to be connected to a voltage ADC.
When an io-channel measures the output voltage of a temperature analog front
end such as a temperature transducer, the interesting measurement is almost
always the corresponding temperature, not the voltage output. This binding
describes such a circuit.
The general transfer function here is (using SI units)
V(T) = Rsense * Isense(T)
T = (Isense(T) / alpha) + offset
T = 1 / (Rsense * alpha) * (V + offset * Rsense * alpha)
When using a temperature to voltage transducer, Rsense is set to 1.
The following circuits show a temperature to current and a temperature to
voltage transducer that can be used with this binding.
VCC
-----
|
+---+---+
| AD590 | VCC
+---+---+ -----
| |
V proportional to T +----+----+
| D+ --+ |
+---- Vout | LTC2997 +--- Vout
| D- --+ |
+---+----+ +---------+
| Rsense | |
+---+----+ -----
| GND
-----
GND
properties:
compatible:
const: temperature-transducer
io-channels:
maxItems: 1
description: |
Channel node of a voltage io-channel.
'#io-channel-cells':
const: 0
sense-offset-millicelsius:
description: |
Temperature offset.
This offset is commonly used to convert from Kelvins to degrees Celsius.
In that case, sense-offset-millicelsius would be set to <(-273150)>.
default: 0
sense-resistor-ohms:
description: |
The sense resistor.
By default sense-resistor-ohms cancels out the resistor making the
circuit behave like a temperature transducer.
default: 1
alpha-ppm-per-celsius:
description: |
Sometimes referred to as output gain, slope, or temperature coefficient.
alpha is expressed in parts per million which can be micro-amps per
degrees Celsius or micro-volts per degrees Celsius. The is the main
characteristic of a temperature transducer and should be stated in the
datasheet.
additionalProperties: false
required:
- compatible
- io-channels
- alpha-ppm-per-celsius
examples:
- |
ad950: temperature-sensor-0 {
compatible = "temperature-transducer";
#io-channel-cells = <0>;
io-channels = <&temp_adc 3>;
sense-offset-millicelsius = <(-273150)>; /* Kelvin to degrees Celsius */
sense-resistor-ohms = <8060>;
alpha-ppm-per-celsius = <1>; /* 1 uA/K */
};
- |
znq_tmp: temperature-sensor-1 {
compatible = "temperature-transducer";
#io-channel-cells = <0>;
io-channels = <&temp_adc 2>;
sense-offset-millicelsius = <(-273150)>; /* Kelvin to degrees Celsius */
alpha-ppm-per-celsius = <4000>; /* 4 mV/K */
};
...
Documentation/devicetree/bindings/iio/amplifiers/adi,ada4250.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/amplifiers/adi,ada4250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADA4250 Programmable Gain Instrumentation Amplifier
maintainers:
- Antoniu Miclaus <antoniu.miclaus@analog.com>
description: |
Precision Low Power, 110kHz, 26uA, Programmable Gain Instrumentation Amplifier.
properties:
compatible:
enum:
- adi,ada4250
reg:
maxItems: 1
avdd-supply: true
adi,refbuf-enable:
description:
Enable internal buffer to drive the reference pin.
type: boolean
spi-max-frequency: true
required:
- compatible
- reg
- avdd-supply
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
amplifier@0 {
compatible = "adi,ada4250";
reg = <0>;
avdd-supply = <&avdd>;
};
};
...
Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,ltc2688.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices LTC2688 DAC
maintainers:
- Nuno Sá <nuno.sa@analog.com>
description: |
Analog Devices LTC2688 16 channel, 16 bit, +-15V DAC
https://www.analog.com/media/en/technical-documentation/data-sheets/ltc2688.pdf
properties:
compatible:
enum:
- adi,ltc2688
reg:
maxItems: 1
vcc-supply:
description: Analog Supply Voltage Input.
iovcc-supply:
description: Digital Input/Output Supply Voltage.
vref-supply:
description:
Reference Input/Output. The voltage at the REF pin sets the full-scale
range of all channels. If not provided the internal reference is used and
also provided on the VREF pin".
clr-gpios:
description:
If specified, it will be asserted during driver probe. As the line is
active low, it should be marked GPIO_ACTIVE_LOW.
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^channel@([0-9]|1[0-5])$":
type: object
properties:
reg:
description: The channel number representing the DAC output channel.
maximum: 15
adi,toggle-mode:
description:
Set the channel as a toggle enabled channel. Toggle operation enables
fast switching of a DAC output between two different DAC codes without
any SPI transaction.
type: boolean
adi,output-range-microvolt:
description: Specify the channel output full scale range.
oneOf:
- items:
- const: 0
- enum: [5000000, 10000000]
- items:
- const: -5000000
- const: 5000000
- items:
- const: -10000000
- const: 10000000
- items:
- const: -15000000
- const: 15000000
adi,overrange:
description: Enable 5% overrange over the selected full scale range.
type: boolean
clocks:
maxItems: 1
adi,toggle-dither-input:
description:
Selects the TGPx pin to be associated with this channel. This setting
only makes sense for toggle or dither enabled channels. If
@adi,toggle-mode is not set and this property is given, the channel is
assumed to be a dither capable channel. Note that multiple channels
can be mapped to the same pin. If this setting is given, the
respective @clock must also be provided. Mappings between this and
input pins
0 - TGP1
1 - TGP2
2 - TGP3
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
dependencies:
adi,toggle-dither-input: [ clocks ]
required:
- reg
required:
- compatible
- reg
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
ltc2688: ltc2688@0 {
compatible = "adi,ltc2688";
reg = <0>;
vcc-supply = <&vcc>;
iovcc-supply = <&vcc>;
vref-supply = <&vref>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
adi,toggle-mode;
adi,overrange;
};
channel@1 {
reg = <1>;
adi,output-range-microvolt = <0 10000000>;
clocks = <&clock_tgp3>;
adi,toggle-dither-input = <2>;
};
};
};
...
Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/frequency/adi,admv1014.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADMV1014 Microwave Downconverter
maintainers:
- Antoniu Miclaus <antoniu.miclaus@analog.com>
description: |
Wideband, microwave downconverter optimized for point to point microwave
radio designs operating in the 24 GHz to 44 GHz frequency range.
https://www.analog.com/en/products/admv1014.html
properties:
compatible:
enum:
- adi,admv1014
reg:
maxItems: 1
spi-max-frequency:
maximum: 1000000
clocks:
maxItems: 1
clock-names:
items:
- const: lo_in
description:
External clock that provides the Local Oscilator input.
vcm-supply:
description:
Common-mode voltage regulator.
vcc-if-bb-supply:
description:
BB and IF supply voltage regulator.
vcc-vga-supply:
description:
RF Amplifier supply voltage regulator.
vcc-vva-supply:
description:
VVA Control Circuit supply voltage regulator.
vcc-lna-3p3-supply:
description:
Low Noise Amplifier 3.3V supply voltage regulator.
vcc-lna-1p5-supply:
description:
Low Noise Amplifier 1.5V supply voltage regulator.
vcc-bg-supply:
description:
Band Gap Circuit supply voltage regulator.
vcc-quad-supply:
description:
Quadruple supply voltage regulator.
vcc-mixer-supply:
description:
Mixer supply voltage regulator.
adi,input-mode:
description:
Select the input mode.
iq - in-phase quadrature (I/Q) input
if - complex intermediate frequency (IF) input
enum: [iq, if]
adi,detector-enable:
description:
Digital Rx Detector Enable. The Square Law Detector output is
available at output pin VDET.
type: boolean
adi,p1db-compensation-enable:
description:
Turn on bits to optimize P1dB.
type: boolean
adi,quad-se-mode:
description:
Switch the LO path from differential to single-ended operation.
se-neg - Single-Ended Mode, Negative Side Disabled.
se-pos - Single-Ended Mode, Positive Side Disabled.
diff - Differential Mode.
enum: [se-neg, se-pos, diff]
required:
- compatible
- reg
- clocks
- clock-names
- vcm-supply
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
converter@0 {
compatible = "adi,admv1014";
reg = <0>;
spi-max-frequency = <1000000>;
clocks = <&admv1014_lo>;
clock-names = "lo_in";
vcm-supply = <&vcm>;
vcc-if-bb-supply = <&vcc_if_bb>;
vcc-vga-supply = <&vcc_vga>;
vcc-vva-supply = <&vcc_vva>;
vcc-lna-3p3-supply = <&vcc_lna_3p3>;
vcc-lna-1p5-supply = <&vcc_lna_1p5>;
vcc-bg-supply = <&vcc_bg>;
vcc-quad-supply = <&vcc_quad>;
vcc-mixer-supply = <&vcc_mixer>;
adi,quad-se-mode = "diff";
adi,detector-enable;
adi,p1db-compensation-enable;
};
};
...
Documentation/devicetree/bindings/iio/frequency/adi,admv4420.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/frequency/adi,admv4420.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADMV4420 K Band Downconverter
maintainers:
- Cristian Pop <cristian.pop@analog.com>
description:
The ADMV4420 is a highly integrated, double balanced, active
mixer with an integrated fractional-N synthesizer, ideally suited
for next generation K band satellite communications
properties:
compatible:
enum:
- adi,admv4420
reg:
maxItems: 1
spi-max-frequency:
maximum: 1000000
adi,lo-freq-khz:
description: LO Frequency
$ref: /schemas/types.yaml#/definitions/uint32
adi,ref-ext-single-ended-en:
description: External reference selected.
type: boolean
required:
- compatible
- reg
additionalProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
mixer@0 {
compatible = "adi,admv4420";
reg = <0>;
spi-max-frequency = <1000000>;
adi,lo-freq-khz = <16750000>;
adi,ref-ext-single-ended-en;
};
};
...
Documentation/devicetree/bindings/iio/proximity/semtech,sx9324.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/proximity/semtech,sx9324.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Semtech's SX9324 capacitive proximity sensor
maintainers:
- Gwendal Grignou <gwendal@chromium.org>
- Daniel Campello <campello@chromium.org>
description: |
Semtech's SX9324 proximity sensor.
properties:
compatible:
const: semtech,sx9324
reg:
maxItems: 1
interrupts:
description:
Generated by device to announce preceding read request has finished
and data is available or that a close/far proximity event has happened.
maxItems: 1
vdd-supply:
description: Main power supply
svdd-supply:
description: Host interface power supply
"#io-channel-cells":
const: 1
semtech,ph0-pin:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Array of 3 entries. Index represent the id of the CS pin.
Value indicates how each CS pin is used during phase 0.
Each of the 3 pins have the following value -
0 : unused (high impedance)
1 : measured input
2 : dynamic shield
3 : grounded.
For instance, CS0 measured, CS1 shield and CS2 ground is [1, 2, 3]
items:
enum: [ 0, 1, 2, 3 ]
minItems: 3
maxItems: 3
semtech,ph1-pin:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: Same as ph0-pin for phase 1.
items:
enum: [ 0, 1, 2, 3 ]
minItems: 3
maxItems: 3
semtech,ph2-pin:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: Same as ph0-pin for phase 2.
items:
enum: [ 0, 1, 2, 3 ]
minItems: 3
maxItems: 3
semtech,ph3-pin:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: Same as ph0-pin for phase 3.
items:
enum: [ 0, 1, 2, 3 ]
minItems: 3
maxItems: 3
semtech,ph01-resolution:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16, 32, 64, 128, 256, 512, 1024]
description:
Capacitance measurement resolution. For phase 0 and 1.
Higher the number, higher the resolution.
default: 128
semtech,ph23-resolution:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16, 32, 64, 128, 256, 512, 1024]
description:
Capacitance measurement resolution. For phase 2 and 3
default: 128
semtech,startup-sensor:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
default: 0
description: |
Phase used for start-up proximity detection.
It is used when we enable a phase to remove static offset and measure
only capacitance changes introduced by the user.
semtech,ph01-proxraw-strength:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
default: 1
description:
PROXRAW filter strength for phase 0 and 1. A value of 0 represents off,
and other values represent 1-1/2^N.
semtech,ph23-proxraw-strength:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
default: 1
description:
Same as proxraw-strength01, for phase 2 and 3.
semtech,avg-pos-strength:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 16, 64, 128, 256, 512, 1024, 4294967295]
default: 16
description: |
Average positive filter strength. A value of 0 represents off and
UINT_MAX (4294967295) represents infinite. Other values
represent 1-1/N.
required:
- compatible
- reg
- "#io-channel-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
proximity@28 {
compatible = "semtech,sx9324";
reg = <0x28>;
interrupt-parent = <&pio>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW 5>;
vdd-supply = <&pp3300_a>;
svdd-supply = <&pp1800_prox>;
#io-channel-cells = <1>;
semtech,ph0-pin = <1 2 3>;
semtech,ph1-pin = <3 2 1>;
semtech,ph2-pin = <1 2 3>;
semtech,ph3-pin = <3 2 1>;
semtech,ph01-resolution = <256>;
semtech,ph23-resolution = <256>;
semtech,startup-sensor = <1>;
semtech,ph01-proxraw-strength = <2>;
semtech,ph23-proxraw-strength = <2>;
semtech,avg-pos-strength = <64>;
};
};
Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/proximity/semtech,sx9360.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Semtech's SX9360 capacitive proximity sensor
maintainers:
- Gwendal Grignou <gwendal@chromium.org>
- Daniel Campello <campello@chromium.org>
description: |
Semtech's SX9360 proximity sensor.
properties:
compatible:
const: semtech,sx9360
reg:
maxItems: 1
interrupts:
description:
Generated by device to announce preceding read request has finished
and data is available or that a close/far proximity event has happened.
maxItems: 1
vdd-supply:
description: Main power supply
svdd-supply:
description: Host interface power supply
"#io-channel-cells":
const: 1
semtech,resolution:
$ref: /schemas/types.yaml#/definitions/uint32-array
enum: [8, 16, 32, 64, 128, 256, 512, 1024]
description:
Capacitance measurement resolution. For both phases, "reference" and
"measurement". Higher the number, higher the resolution.
default: 128
semtech,proxraw-strength:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
default: 1
description:
PROXRAW filter strength for both phases. A value of 0 represents off,
and other values represent 1-1/2^N.
semtech,avg-pos-strength:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 16, 64, 128, 256, 512, 1024, 4294967295]
default: 16
description: |
Average positive filter strength. A value of 0 represents off and
UINT_MAX (4294967295) represents infinite. Other values
represent 1-1/N.
required:
- compatible
- reg
- "#io-channel-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
proximity@28 {
compatible = "semtech,sx9360";
reg = <0x28>;
interrupt-parent = <&pio>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW 5>;
vdd-supply = <&pp3300_a>;
svdd-supply = <&pp1800_prox>;
#io-channel-cells = <1>;
semtech,resolution = <256>;
semtech,proxraw-strength = <2>;
semtech,avg-pos-strength = <64>;
};
};
Documentation/devicetree/bindings/iio/st,st-sensors.yaml
View file @ 02e2af20
......@@ -46,6 +46,9 @@ properties:
- st,lsm330d-accel
- st,lsm330dl-accel
- st,lsm330dlc-accel
- description: Silan Accelerometers
enum:
- silan,sc7a20
- description: STMicroelectronics Gyroscopes
enum:
- st,l3g4200d-gyro
......
Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
View file @ 02e2af20
......@@ -26,7 +26,6 @@ properties:
- qcom,msm8939-bimc
- qcom,msm8939-pcnoc
- qcom,msm8939-snoc
- qcom,msm8939-snoc-mm
- qcom,msm8996-a0noc
- qcom,msm8996-a1noc
- qcom,msm8996-a2noc
......@@ -80,7 +79,6 @@ allOf:
- qcom,msm8939-bimc
- qcom,msm8939-pcnoc
- qcom,msm8939-snoc
- qcom,msm8939-snoc-mm
- qcom,msm8996-a1noc
- qcom,msm8996-a2noc
- qcom,msm8996-bimc
......@@ -107,6 +105,37 @@ allOf:
- description: Bus Clock
- description: Bus A Clock
# Child node's properties
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
description:
snoc-mm is a child of snoc, sharing snoc's register address space.
properties:
compatible:
enum:
- qcom,msm8939-snoc-mm
'#interconnect-cells':
const: 1
clock-names:
items:
- const: bus
- const: bus_a
clocks:
items:
- description: Bus Clock
- description: Bus A Clock
required:
- compatible
- '#interconnect-cells'
- clock-names
- clocks
- if:
properties:
compatible:
......
Documentation/devicetree/bindings/mfd/delta,tn48m-cpld.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/delta,tn48m-cpld.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Delta Networks TN48M CPLD controller
maintainers:
- Robert Marko <robert.marko@sartura.hr>
description: |
Lattice CPLD onboard the TN48M switches is used for system
management.
It provides information about the hardware model, revision,
PSU status etc.
It is also being used as a GPIO expander and reset controller
for the switch MAC-s and other peripherals.
properties:
compatible:
const: delta,tn48m-cpld
reg:
description:
I2C device address.
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
patternProperties:
"^gpio(@[0-9a-f]+)?$":
$ref: ../gpio/delta,tn48m-gpio.yaml
"^reset-controller?$":
$ref: ../reset/delta,tn48m-reset.yaml
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
cpld@41 {
compatible = "delta,tn48m-cpld";
reg = <0x41>;
#address-cells = <1>;
#size-cells = <0>;
gpio@31 {
compatible = "delta,tn48m-gpo";
reg = <0x31>;
gpio-controller;
#gpio-cells = <2>;
};
gpio@3a {
compatible = "delta,tn48m-gpi";
reg = <0x3a>;
gpio-controller;
#gpio-cells = <2>;
};
gpio@40 {
compatible = "delta,tn48m-gpi";
reg = <0x40>;
gpio-controller;
#gpio-cells = <2>;
};
reset-controller {
compatible = "delta,tn48m-reset";
#reset-cells = <1>;
};
};
};
Documentation/devicetree/bindings/misc/qcom,fastrpc.txt
View file @ 02e2af20
......@@ -17,6 +17,16 @@ other tasks.
Definition: should specify the dsp domain name this fastrpc
corresponds to. must be one of this: "adsp", "mdsp", "sdsp", "cdsp"
- qcom,non-secure-domain:
Usage: required
Value type: <boolean>
Definition: Property to specify that dsp domain is non-secure.
- qcom,vmids:
Usage: optional
Value type: <u32 array>
Definition: Virtual machine IDs for remote processor.
- #address-cells
Usage: required
Value type: <u32>
......
Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml
View file @ 02e2af20
......@@ -20,6 +20,7 @@ properties:
- const: allwinner,sun7i-a20-sid
- const: allwinner,sun8i-a83t-sid
- const: allwinner,sun8i-h3-sid
- const: allwinner,sun20i-d1-sid
- const: allwinner,sun50i-a64-sid
- items:
- const: allwinner,sun50i-a100-sid
......
Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml
View file @ 02e2af20
......@@ -14,6 +14,8 @@ description: |
NVRAM can be accessed on Broadcom BCM47xx MIPS and Northstar ARM Cortex-A9
devices usiong I/O mapped memory.
NVRAM variables can be defined as NVMEM device subnodes.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
......@@ -27,11 +29,30 @@ properties:
reg:
maxItems: 1
board_id:
type: object
description: Board identification name
et0macaddr:
type: object
description: First Ethernet interface's MAC address
et1macaddr:
type: object
description: Second Ethernet interface's MAC address
et2macaddr:
type: object
description: Third Ethernet interface's MAC address
unevaluatedProperties: false
examples:
- |
nvram@1eff0000 {
compatible = "brcm,nvram";
reg = <0x1eff0000 0x10000>;
compatible = "brcm,nvram";
reg = <0x1eff0000 0x10000>;
mac: et0macaddr {
};
};
Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/fsl,layerscape-sfp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Layerscape Security Fuse Processor
maintainers:
- Michael Walle <michael@walle.cc>
description: |
SFP is the security fuse processor which among other things provide a
unique identifier per part.
allOf:
- $ref: "nvmem.yaml#"
properties:
compatible:
enum:
- fsl,ls1028a-sfp
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
efuse@1e80000 {
compatible = "fsl,ls1028a-sfp";
reg = <0x1e80000 0x8000>;
};
Documentation/devicetree/bindings/nvmem/nvmem.yaml
View file @ 02e2af20
......@@ -60,9 +60,6 @@ patternProperties:
description:
Size in bit within the address range specified by reg.
required:
- reg
additionalProperties: true
examples:
......
Documentation/devicetree/bindings/nvmem/sunplus,sp7021-ocotp.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/sunplus,sp7021-ocotp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: On-Chip OTP Memory for Sunplus SP7021
maintainers:
- Vincent Shih <vincent.sunplus@gmail.com>
allOf:
- $ref: "nvmem.yaml#"
properties:
compatible:
const: sunplus,sp7021-ocotp
reg:
maxItems: 2
reg-names:
items:
- const: hb_gpio
- const: otprx
clocks:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
thermal-calibration:
type: object
description: thermal calibration values
disconnect-voltage:
type: object
description: disconnect voltages of usb2 port 0 and port 1
mac-address0:
type: object
description: MAC address of ethernet port 0
mac-address1:
type: object
description: MAC address of ethernet port 1
required:
- compatible
- reg
- reg-names
- clocks
unevaluatedProperties: false
examples:
- |
otp: otp@9c00af00 {
compatible = "sunplus,sp7021-ocotp";
reg = <0x9c00af00 0x34>, <0x9c00af80 0x58>;
reg-names = "hb_gpio", "otprx";
clocks = <&clkc 0x15>;
#address-cells = <1>;
#size-cells = <1>;
therm_calib: thermal-calibration@14 {
reg = <0x14 0x3>;
};
disc_vol: disconnect-voltage@18 {
reg = <0x18 0x2>;
};
mac_addr0: mac-address0@34 {
reg = <0x34 0x6>;
};
mac_addr1: mac-address1@3a {
reg = <0x3a 0x6>;
};
};
...
Documentation/devicetree/bindings/peci/peci-aspeed.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/peci/peci-aspeed.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed PECI Bus Device Tree Bindings
maintainers:
- Iwona Winiarska <iwona.winiarska@intel.com>
- Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
allOf:
- $ref: peci-controller.yaml#
properties:
compatible:
enum:
- aspeed,ast2400-peci
- aspeed,ast2500-peci
- aspeed,ast2600-peci
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
description:
Clock source for PECI controller. Should reference the external
oscillator clock.
maxItems: 1
resets:
maxItems: 1
cmd-timeout-ms:
minimum: 1
maximum: 1000
default: 1000
clock-frequency:
description:
The desired operation frequency of PECI controller in Hz.
minimum: 2000
maximum: 2000000
default: 1000000
required:
- compatible
- reg
- interrupts
- clocks
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/ast2600-clock.h>
peci-controller@1e78b000 {
compatible = "aspeed,ast2600-peci";
reg = <0x1e78b000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>;
resets = <&syscon ASPEED_RESET_PECI>;
cmd-timeout-ms = <1000>;
clock-frequency = <1000000>;
};
...
Documentation/devicetree/bindings/peci/peci-controller.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/peci/peci-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic Device Tree Bindings for PECI
maintainers:
- Iwona Winiarska <iwona.winiarska@intel.com>
description:
PECI (Platform Environment Control Interface) is an interface that provides a
communication channel from Intel processors and chipset components to external
monitoring or control devices.
properties:
$nodename:
pattern: "^peci-controller(@.*)?$"
cmd-timeout-ms:
description:
Command timeout in units of ms.
additionalProperties: true
examples:
- |
peci-controller@1e78b000 {
reg = <0x1e78b000 0x100>;
cmd-timeout-ms = <500>;
};
...
Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
View file @ 02e2af20
......@@ -15,7 +15,9 @@ properties:
const: 1
compatible:
const: allwinner,sun50i-a64-usb-phy
enum:
- allwinner,sun20i-d1-usb-phy
- allwinner,sun50i-a64-usb-phy
reg:
items:
......
Documentation/devicetree/bindings/phy/cdns,dphy-rx.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence DPHY Rx Device Tree Bindings
maintainers:
- Pratyush Yadav <p.yadav@ti.com>
properties:
compatible:
items:
- const: cdns,dphy-rx
reg:
maxItems: 1
"#phy-cells":
const: 0
power-domains:
maxItems: 1
required:
- compatible
- reg
- "#phy-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/ti,sci_pm_domain.h>
dphy0: phy@4580000 {
compatible = "cdns,dphy-rx";
reg = <0x4580000 0x1100>;
#phy-cells = <0>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
};
Documentation/devicetree/bindings/phy/cdns,dphy.txt deleted 100644 → 0
View file @ ff61bc81
Cadence DPHY
============
Cadence DPHY block.
Required properties:
- compatible: should be set to "cdns,dphy".
- reg: physical base address and length of the DPHY registers.
- clocks: DPHY reference clocks.
- clock-names: must contain "psm" and "pll_ref".
- #phy-cells: must be set to 0.
Example:
dphy0: dphy@fd0e0000{
compatible = "cdns,dphy";
reg = <0x0 0xfd0e0000 0x0 0x1000>;
clocks = <&psm_clk>, <&pll_ref_clk>;
clock-names = "psm", "pll_ref";
#phy-cells = <0>;
};
Documentation/devicetree/bindings/phy/cdns,dphy.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence DPHY Device Tree Bindings
maintainers:
- Pratyush Yadav <p.yadav@ti.com>
properties:
compatible:
items:
- const: cdns,dphy
reg:
maxItems: 1
clocks:
items:
- description: PMA state machine clock
- description: PLL reference clock
clock-names:
items:
- const: psm
- const: pll_ref
"#phy-cells":
const: 0
power-domains:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- "#phy-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/soc/ti,sci_pm_domain.h>
dphy0: phy@fd0e0000{
compatible = "cdns,dphy";
reg = <0xfd0e0000 0x1000>;
clocks = <&psm_clk>, <&pll_ref_clk>;
clock-names = "psm", "pll_ref";
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
#phy-cells = <0>;
};
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
View file @ 02e2af20
......@@ -80,6 +80,8 @@ properties:
- mediatek,mt2712-tphy
- mediatek,mt7629-tphy
- mediatek,mt8183-tphy
- mediatek,mt8186-tphy
- mediatek,mt8192-tphy
- const: mediatek,generic-tphy-v2
- items:
- enum:
......
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
enum:
- rockchip,rk3568-naneng-combphy
reg:
maxItems: 1
clocks:
items:
- description: reference clock
- description: apb clock
- description: pipe clock
clock-names:
items:
- const: ref
- const: apb
- const: pipe
resets:
items:
- description: exclusive PHY reset line
rockchip,enable-ssc:
type: boolean
description:
The option SSC can be enabled for U3, SATA and PCIE.
Most commercially available platforms use SSC to reduce EMI.
rockchip,ext-refclk:
type: boolean
description:
Many PCIe connections, especially backplane connections,
require a synchronous reference clock between the two link partners.
To achieve this a common clock source, referred to as REFCLK in
the PCI Express Card Electromechanical Specification,
should be used by both ends of the PCIe link.
In PCIe mode one can choose to use an internal or an external reference
clock.
By default the internal clock is selected. The PCIe PHY provides a 100MHz
differential clock output(optional with SSC) for system applications.
When selecting this option an externally 100MHz differential
reference clock needs to be provided to the PCIe PHY.
rockchip,pipe-grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Some additional phy settings are accessed through GRF regs.
rockchip,pipe-phy-grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Some additional pipe settings are accessed through GRF regs.
"#phy-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- resets
- rockchip,pipe-grf
- rockchip,pipe-phy-grf
- "#phy-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3568-cru.h>
pipegrf: syscon@fdc50000 {
compatible = "rockchip,rk3568-pipe-grf", "syscon";
reg = <0xfdc50000 0x1000>;
};
pipe_phy_grf0: syscon@fdc70000 {
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
reg = <0xfdc70000 0x1000>;
};
combphy0: phy@fe820000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0xfe820000 0x100>;
clocks = <&pmucru CLK_PCIEPHY0_REF>,
<&cru PCLK_PIPEPHY0>,
<&cru PCLK_PIPE>;
clock-names = "ref", "apb", "pipe";
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_PIPEPHY0>;
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
#phy-cells = <1>;
};
Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
View file @ 02e2af20
......@@ -16,7 +16,9 @@ description:
properties:
compatible:
const: qcom,sc8180x-edp-phy
enum:
- qcom,sc7280-edp-phy
- qcom,sc8180x-edp-phy
reg:
items:
......
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
View file @ 02e2af20
......@@ -32,6 +32,7 @@ properties:
- qcom,sc8180x-qmp-pcie-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8180x-qmp-usb3-phy
- qcom,sc8280xp-qmp-ufs-phy
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdm845-qmp-ufs-phy
......@@ -280,6 +281,8 @@ allOf:
- qcom,sdm845-qmp-ufs-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8250-qmp-ufs-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
then:
properties:
clocks:
......
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
View file @ 02e2af20
......@@ -19,6 +19,7 @@ properties:
- items:
- enum:
- qcom,ipq8074-qusb2-phy
- qcom,msm8953-qusb2-phy
- qcom,msm8996-qusb2-phy
- qcom,msm8998-qusb2-phy
- qcom,qcm2290-qusb2-phy
......
Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt deleted 100644 → 0
View file @ ff61bc81
Qualcomm's USB HS PHY
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the
following:
"qcom,usb-hs-phy-apq8064"
"qcom,usb-hs-phy-msm8226"
"qcom,usb-hs-phy-msm8916"
"qcom,usb-hs-phy-msm8974"
- #phy-cells:
Usage: required
Value type: <u32>
Definition: Should contain 0
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: Should contain clock specifier for the reference and sleep
clocks
- clock-names:
Usage: required
Value type: <stringlist>
Definition: Should contain "ref" and "sleep" for the reference and sleep
clocks respectively
- resets:
Usage: required
Value type: <prop-encoded-array>
Definition: Should contain the phy and POR resets
- reset-names:
Usage: required
Value type: <stringlist>
Definition: Should contain "phy" and "por" for the phy and POR resets
respectively
- v3p3-supply:
Usage: required
Value type: <phandle>
Definition: Should contain a reference to the 3.3V supply
- v1p8-supply:
Usage: required
Value type: <phandle>
Definition: Should contain a reference to the 1.8V supply
- extcon:
Usage: optional
Value type: <prop-encoded-array>
Definition: Should contain the vbus extcon
- qcom,init-seq:
Usage: optional
Value type: <u8 array>
Definition: Should contain a sequence of ULPI address and value pairs to
program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related
to Device Mode Eye Diagram test. The addresses are offsets
from the ULPI_EXT_VENDOR_SPECIFIC address, for example,
<0x1 0x53> would mean "write the value 0x53 to address 0x81".
EXAMPLE
otg: usb-controller {
ulpi {
phy {
compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy";
#phy-cells = <0>;
clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ref", "sleep";
resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
reset-names = "phy", "por";
v3p3-supply = <&pm8941_l24>;
v1p8-supply = <&pm8941_l6>;
extcon = <&smbb>;
qcom,init-seq = /bits/ 8 <0x1 0x63>;
};
};
};
Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm's USB HS PHY binding description
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
if:
properties:
compatible:
contains:
const: qcom,usb-hs-phy-apq8064
then:
properties:
resets:
maxItems: 1
reset-names:
const: por
else:
properties:
resets:
minItems: 2
maxItems: 2
reset-names:
items:
- const: phy
- const: por
properties:
compatible:
items:
- enum:
- qcom,usb-hs-phy-apq8064
- qcom,usb-hs-phy-msm8226
- qcom,usb-hs-phy-msm8916
- qcom,usb-hs-phy-msm8974
- const: qcom,usb-hs-phy
clocks:
minItems: 2
maxItems: 2
clock-names:
maxItems: 2
contains:
items:
- const: ref
- const: sleep
resets: true
reset-names: true
v1p8-supply: true
v3p3-supply: true
extcon: true
"#phy-cells":
const: 0
qcom,init-seq:
$ref: /schemas/types.yaml#/definitions/uint8-matrix
description: >
Sequence of ULPI address and value pairs to
program into the ULPI_EXT_VENDOR_SPECIFIC area.
This is related to Device Mode Eye Diagram test.
maxItems: 32 # no hard limit
items:
items:
- description: >
the address is offset from the ULPI_EXT_VENDOR_SPECIFIC address
- description: value
required:
- clocks
- clock-names
- resets
- reset-names
- "#phy-cells"
additionalProperties: false
examples:
- |
otg: usb-controller {
ulpi {
phy {
compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy";
#phy-cells = <0>;
clocks = <&clk 0>, <&clk 258>;
clock-names = "ref", "sleep";
resets = <&gcc 10>, <&otg 0>;
reset-names = "phy", "por";
v3p3-supply = <&pm8941_l24>;
v1p8-supply = <&pm8941_l6>;
extcon = <&smbb>;
qcom,init-seq = /bits/ 8 <0x1 0x63>;
};
};
};
Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml
View file @ 02e2af20
......@@ -15,8 +15,11 @@ description: |
properties:
compatible:
enum:
- qcom,usb-snps-hs-5nm-phy
- qcom,usb-snps-hs-7nm-phy
- qcom,sc7280-usb-hs-phy
- qcom,sc8180x-usb-hs-phy
- qcom,sc8280xp-usb-hs-phy
- qcom,sm8150-usb-hs-phy
- qcom,sm8250-usb-hs-phy
- qcom,sm8350-usb-hs-phy
......
Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
View file @ 02e2af20
......@@ -33,7 +33,8 @@ properties:
- items:
- enum:
- renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
- const: renesas,rzg2l-usb2-phy # RZ/G2L family
- renesas,usb2-phy-r9a07g054 # RZ/V2L
- const: renesas,rzg2l-usb2-phy
reg:
maxItems: 1
......
Documentation/devicetree/bindings/phy/samsung,dp-video-phy.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,dp-video-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC DisplayPort PHY
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Marek Szyprowski <m.szyprowski@samsung.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
properties:
compatible:
enum:
- samsung,exynos5250-dp-video-phy
- samsung,exynos5420-dp-video-phy
"#phy-cells":
const: 0
samsung,pmu-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to PMU system controller interface.
required:
- compatible
- "#phy-cells"
- samsung,pmu-syscon
additionalProperties: false
examples:
- |
phy {
compatible = "samsung,exynos5420-dp-video-phy";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <0>;
};
Documentation/devicetree/bindings/phy/samsung,exynos5250-sata-phy.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,exynos5250-sata-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos5250 SoC SATA PHY
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Marek Szyprowski <m.szyprowski@samsung.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
properties:
compatible:
const: samsung,exynos5250-sata-phy
clocks:
maxItems: 1
clock-names:
items:
- const: sata_phyctrl
"#phy-cells":
const: 0
reg:
maxItems: 1
samsung,syscon-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to PMU system controller interface.
samsung,exynos-sataphy-i2c-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to I2C SATA interface.
required:
- compatible
- clocks
- clock-names
- "#phy-cells"
- reg
- samsung,syscon-phandle
- samsung,exynos-sataphy-i2c-phandle
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
phy@12170000 {
compatible = "samsung,exynos5250-sata-phy";
reg = <0x12170000 0x1ff>;
clocks = <&clock CLK_SATA_PHYCTRL>;
clock-names = "sata_phyctrl";
#phy-cells = <0>;
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
};
Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,mipi-video-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S5P/Exynos SoC MIPI CSIS/DSIM DPHY
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Marek Szyprowski <m.szyprowski@samsung.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
description: |
For samsung,s5pv210-mipi-video-phy compatible PHYs the second cell in the
PHY specifier identifies the PHY and its meaning is as follows::
0 - MIPI CSIS 0,
1 - MIPI DSIM 0,
2 - MIPI CSIS 1,
3 - MIPI DSIM 1.
samsung,exynos5420-mipi-video-phy and samsung,exynos5433-mipi-video-phy
support additional fifth PHY::
4 - MIPI CSIS 2.
properties:
compatible:
enum:
- samsung,s5pv210-mipi-video-phy
- samsung,exynos5420-mipi-video-phy
- samsung,exynos5433-mipi-video-phy
"#phy-cells":
const: 1
syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to PMU system controller interface, valid only for
samsung,s5pv210-mipi-video-phy and samsung,exynos5420-mipi-video-phy.
samsung,pmu-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to PMU system controller interface, valid for
samsung,exynos5433-mipi-video-phy.
samsung,disp-sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to DISP system controller interface, valid for
samsung,exynos5433-mipi-video-phy.
samsung,cam0-sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to CAM0 system controller interface, valid for
samsung,exynos5433-mipi-video-phy.
samsung,cam1-sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to CAM1 system controller interface, valid for
samsung,exynos5433-mipi-video-phy.
required:
- compatible
- "#phy-cells"
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,s5pv210-mipi-video-phy
- samsung,exynos5420-mipi-video-phy
then:
properties:
samsung,pmu-syscon: false
samsung,disp-sysreg: false
samsung,cam0-sysreg: false
samsung,cam1-sysreg: false
required:
- syscon
else:
properties:
syscon: false
required:
- samsung,pmu-syscon
- samsung,disp-sysreg
- samsung,cam0-sysreg
- samsung,cam1-sysreg
additionalProperties: false
examples:
- |
phy {
compatible = "samsung,exynos5433-mipi-video-phy";
#phy-cells = <1>;
samsung,pmu-syscon = <&pmu_system_controller>;
samsung,cam0-sysreg = <&syscon_cam0>;
samsung,cam1-sysreg = <&syscon_cam1>;
samsung,disp-sysreg = <&syscon_disp>;
};
- |
phy {
compatible = "samsung,s5pv210-mipi-video-phy";
syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S5P/Exynos SoC USB 2.0 PHY
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Marek Szyprowski <m.szyprowski@samsung.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
description: |
The first phandle argument in the PHY specifier identifies the PHY, its
meaning is compatible dependent. For the currently supported SoCs (Exynos4210
and Exynos4212) it is as follows::
0 - USB device ("device"),
1 - USB host ("host"),
2 - HSIC0 ("hsic0"),
3 - HSIC1 ("hsic1"),
Exynos3250 has only USB device phy available as phy 0.
Exynos4210 and Exynos4212 use mode switching and require that mode switch
register is supplied.
properties:
compatible:
enum:
- samsung,exynos3250-usb2-phy
- samsung,exynos4210-usb2-phy
- samsung,exynos4x12-usb2-phy
- samsung,exynos5250-usb2-phy
- samsung,exynos5420-usb2-phy
- samsung,s5pv210-usb2-phy
clocks:
items:
- description: PHY module gate clock.
- description: Reference rate clock of PHY module.
clock-names:
items:
- const: phy
- const: ref
"#phy-cells":
const: 1
reg:
maxItems: 1
samsung,pmureg-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to PMU system controller interface.
samsung,sysreg-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to system registers interface.
vbus-supply:
description:
VBUS power source.
required:
- compatible
- clocks
- clock-names
- "#phy-cells"
- reg
- samsung,pmureg-phandle
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos4x12-usb2-phy
- samsung,exynos5250-usb2-phy
- samsung,exynos5420-usb2-phy
then:
required:
- samsung,sysreg-phandle
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5420.h>
phy@12130000 {
compatible = "samsung,exynos5420-usb2-phy";
reg = <0x12130000 0x100>;
#phy-cells = <1>;
clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
clock-names = "phy", "ref";
samsung,sysreg-phandle = <&sysreg_system_controller>;
samsung,pmureg-phandle = <&pmu_system_controller>;
};
Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Marek Szyprowski <m.szyprowski@samsung.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
description: |
For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
compatible PHYs, the second cell in the PHY specifier identifies the
PHY id, which is interpreted as follows::
0 - UTMI+ type phy,
1 - PIPE3 type phy.
For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
properties:
compatible:
enum:
- samsung,exynos5250-usbdrd-phy
- samsung,exynos5420-usbdrd-phy
- samsung,exynos5433-usbdrd-phy
- samsung,exynos7-usbdrd-phy
clocks:
minItems: 2
maxItems: 5
clock-names:
minItems: 2
maxItems: 5
description: |
At least two clocks::
- Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
for register access.
- PHY reference clock (usually crystal clock), used for PHY operations,
associated by phy name. It is used to determine bit values for clock
settings register. For Exynos5420 this is given as 'sclk_usbphy30'
in the CMU.
"#phy-cells":
const: 1
port:
$ref: /schemas/graph.yaml#/properties/port
description:
Any connector to the data bus of this controller should be modelled using
the OF graph bindings specified.
reg:
maxItems: 1
samsung,pmu-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to PMU system controller interface.
vbus-supply:
description:
VBUS power source.
vbus-boost-supply:
description:
VBUS Boost 5V power source.
required:
- compatible
- clocks
- clock-names
- "#phy-cells"
- reg
- samsung,pmu-syscon
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5433-usbdrd-phy
- samsung,exynos7-usbdrd-phy
then:
properties:
clocks:
minItems: 5
maxItems: 5
clock-names:
items:
- const: phy
- const: ref
- const: phy_utmi
- const: phy_pipe
- const: itp
else:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: phy
- const: ref
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5420.h>
phy@12100000 {
compatible = "samsung,exynos5420-usbdrd-phy";
reg = <0x12100000 0x100>;
#phy-cells = <1>;
clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
vbus-supply = <&usb300_vbus_reg>;
};
Documentation/devicetree/bindings/phy/samsung-phy.txt deleted 100644 → 0
View file @ ff61bc81
Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
-------------------------------------------------
Required properties:
- compatible : should be one of the listed compatibles:
- "samsung,s5pv210-mipi-video-phy"
- "samsung,exynos5420-mipi-video-phy"
- "samsung,exynos5433-mipi-video-phy"
- #phy-cells : from the generic phy bindings, must be 1;
In case of s5pv210 and exynos5420 compatible PHYs:
- syscon - phandle to the PMU system controller
In case of exynos5433 compatible PHY:
- samsung,pmu-syscon - phandle to the PMU system controller
- samsung,disp-sysreg - phandle to the DISP system registers controller
- samsung,cam0-sysreg - phandle to the CAM0 system registers controller
- samsung,cam1-sysreg - phandle to the CAM1 system registers controller
For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
the PHY specifier identifies the PHY and its meaning is as follows:
0 - MIPI CSIS 0,
1 - MIPI DSIM 0,
2 - MIPI CSIS 1,
3 - MIPI DSIM 1.
"samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
supports additional fifth PHY:
4 - MIPI CSIS 2.
Samsung Exynos SoC series Display Port PHY
-------------------------------------------------
Required properties:
- compatible : should be one of the following supported values:
- "samsung,exynos5250-dp-video-phy"
- "samsung,exynos5420-dp-video-phy"
- samsung,pmu-syscon: phandle for PMU system controller interface, used to
control pmu registers for power isolation.
- #phy-cells : from the generic PHY bindings, must be 0;
Samsung S5P/Exynos SoC series USB PHY
-------------------------------------------------
Required properties:
- compatible : should be one of the listed compatibles:
- "samsung,exynos3250-usb2-phy"
- "samsung,exynos4210-usb2-phy"
- "samsung,exynos4x12-usb2-phy"
- "samsung,exynos5250-usb2-phy"
- "samsung,exynos5420-usb2-phy"
- "samsung,s5pv210-usb2-phy"
- reg : a list of registers used by phy driver
- first and obligatory is the location of phy modules registers
- samsung,sysreg-phandle - handle to syscon used to control the system registers
- samsung,pmureg-phandle - handle to syscon used to control PMU registers
- #phy-cells : from the generic phy bindings, must be 1;
- clocks and clock-names:
- the "phy" clock is required by the phy module, used as a gate
- the "ref" clock is used to get the rate of the clock provided to the
PHY module
Optional properties:
- vbus-supply: power-supply phandle for vbus power source
The first phandle argument in the PHY specifier identifies the PHY, its
meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
and Exynos 4212) it is as follows:
0 - USB device ("device"),
1 - USB host ("host"),
2 - HSIC0 ("hsic0"),
3 - HSIC1 ("hsic1"),
Exynos3250 has only USB device phy available as phy 0.
Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
register is supplied.
Example:
For Exynos 4412 (compatible with Exynos 4212):
usbphy: phy@125b0000 {
compatible = "samsung,exynos4x12-usb2-phy";
reg = <0x125b0000 0x100>;
clocks = <&clock 305>, <&clock 2>;
clock-names = "phy", "ref";
#phy-cells = <1>;
samsung,sysreg-phandle = <&sys_reg>;
samsung,pmureg-phandle = <&pmu_reg>;
};
Then the PHY can be used in other nodes such as:
phy-consumer@12340000 {
phys = <&usbphy 2>;
phy-names = "phy";
};
Refer to DT bindings documentation of particular PHY consumer devices for more
information about required PHYs and the way of specification.
Samsung SATA PHY Controller
---------------------------
SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
Each SATA PHY controller should have its own node.
Required properties:
- compatible : compatible list, contains "samsung,exynos5250-sata-phy"
- reg : offset and length of the SATA PHY register set;
- #phy-cells : must be zero
- clocks : must be exactly one entry
- clock-names : must be "sata_phyctrl"
- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
Example:
sata_phy: sata-phy@12170000 {
compatible = "samsung,exynos5250-sata-phy";
reg = <0x12170000 0x1ff>;
clocks = <&clock 287>;
clock-names = "sata_phyctrl";
#phy-cells = <0>;
samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
samsung,syscon-phandle = <&pmu_syscon>;
};
Device-Tree bindings for sataphy i2c client driver
--------------------------------------------------
Required properties:
compatible: Should be "samsung,exynos-sataphy-i2c"
- reg: I2C address of the sataphy i2c device.
Example:
sata_phy_i2c:sata-phy@38 {
compatible = "samsung,exynos-sataphy-i2c";
reg = <0x38>;
};
Samsung Exynos5 SoC series USB DRD PHY controller
--------------------------------------------------
Required properties:
- compatible : Should be set to one of the following supported values:
- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
- "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC.
- "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
- reg : Register offset and length of USB DRD PHY register set;
- clocks: Clock IDs array as required by the controller
- clock-names: names of clocks correseponding to IDs in the clock property;
Required clocks:
- phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
used for register access.
- ref: PHY's reference clock (usually crystal clock), used for
PHY operations, associated by phy name. It is used to
determine bit values for clock settings register.
For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
- optional clocks: Exynos5433 & Exynos7 SoC has now following additional
gate clocks available:
- phy_pipe: for PIPE3 phy
- phy_utmi: for UTMI+ phy
- itp: for ITP generation
- samsung,pmu-syscon: phandle for PMU system controller interface, used to
control pmu registers for power isolation.
- #phy-cells : from the generic PHY bindings, must be 1;
For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
compatible PHYs, the second cell in the PHY specifier identifies the
PHY id, which is interpreted as follows:
0 - UTMI+ type phy,
1 - PIPE3 type phy,
Example:
usbdrd_phy: usbphy@12100000 {
compatible = "samsung,exynos5250-usbdrd-phy";
reg = <0x12100000 0x100>;
clocks = <&clock 286>, <&clock 1>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
};
- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
'usbdrd_phy' nodes should have numbered alias in the aliases node,
in the form of usbdrdphyN, N = 0, 1... (depending on number of
controllers).
Example:
aliases {
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
Samsung Exynos SoC series PCIe PHY controller
--------------------------------------------------
Required properties:
- compatible : Should be set to "samsung,exynos5440-pcie-phy"
- #phy-cells : Must be zero
- reg : a register used by phy driver.
- First is for phy register, second is for block register.
- reg-names : Must be set to "phy" and "block".
Example:
pcie_phy0: pcie-phy@270000 {
#phy-cells = <0>;
compatible = "samsung,exynos5440-pcie-phy";
reg = <0x270000 0x1000>, <0x271000 0x40>;
reg-names = "phy", "block";
};
Documentation/devicetree/bindings/reserved-memory/google,open-dice.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/reserved-memory/google,open-dice.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Open Profile for DICE Device Tree Bindings
description: |
This binding represents a reserved memory region containing data
generated by the Open Profile for DICE protocol.
See https://pigweed.googlesource.com/open-dice/
maintainers:
- David Brazdil <dbrazdil@google.com>
allOf:
- $ref: "reserved-memory.yaml"
properties:
compatible:
const: google,open-dice
reg:
description: page-aligned region of memory containing DICE data
required:
- compatible
- reg
- no-map
unevaluatedProperties: false
examples:
- |
reserved-memory {
#address-cells = <2>;
#size-cells = <1>;
dice: dice@12340000 {
compatible = "google,open-dice";
reg = <0x00 0x12340000 0x2000>;
no-map;
};
};
Documentation/devicetree/bindings/reset/delta,tn48m-reset.yaml 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/delta,tn48m-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Delta Networks TN48M CPLD reset controller
maintainers:
- Robert Marko <robert.marko@sartura.hr>
description: |
This module is part of the Delta TN48M multi-function device. For more
details see ../mfd/delta,tn48m-cpld.yaml.
Reset controller modules provides resets for the following:
* 88F7040 SoC
* 88F6820 SoC
* 98DX3265 switch MAC-s
* 88E1680 PHY-s
* 88E1512 PHY
* PoE PSE controller
properties:
compatible:
const: delta,tn48m-reset
"#reset-cells":
const: 1
required:
- compatible
- "#reset-cells"
additionalProperties: false
Documentation/devicetree/bindings/soundwire/qcom,sdw.txt
View file @ 02e2af20
......@@ -22,7 +22,19 @@ board specific bus parameters.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the SoundWire Controller IRQ
Definition: should specify the SoundWire Controller core and optional
wake IRQ
- interrupt-names:
Usage: Optional
Value type: boolean
Value type: <stringlist>
Definition: should be "core" for core and "wakeup" for wake interrupt.
- wakeup-source:
Usage: Optional
Value type: boolean
Definition: should specify if SoundWire Controller is wake up capable.
- clock-names:
Usage: required
......
Documentation/devicetree/bindings/trivial-devices.yaml
View file @ 02e2af20
......@@ -167,6 +167,8 @@ properties:
- maxim,ds1803-050
# 100 kOhm digital potentiometer with I2C interface
- maxim,ds1803-100
# 10 kOhm digital potentiometer with I2C interface
- maxim,ds3502
# Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
- maxim,max1237
# Temperature Sensor, I2C interface
......@@ -293,6 +295,8 @@ properties:
- renesas,isl29501
# S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
- samsung,24ad0xd1
# Samsung Exynos SoC SATA PHY I2C device
- samsung,exynos-sataphy-i2c
# Sensirion low power multi-pixel gas sensor with I2C interface
- sensirion,sgpc3
# Sensirion multi-pixel gas sensor with I2C interface
......
Documentation/devicetree/bindings/vendor-prefixes.yaml
View file @ 02e2af20
......@@ -1108,6 +1108,8 @@ patternProperties:
description: Silicon Image
"^silabs,.*":
description: Silicon Laboratories
"^silan,.*":
description: Hangzhou Silan Microelectronics Co., Ltd.
"^silead,.*":
description: Silead Inc.
"^silergy,.*":
......
Documentation/driver-api/driver-model/devres.rst
View file @ 02e2af20
......@@ -368,6 +368,7 @@ MUX
devm_mux_chip_alloc()
devm_mux_chip_register()
devm_mux_control_get()
devm_mux_state_get()
NET
devm_alloc_etherdev()
......
Documentation/driver-api/nvmem.rst
View file @ 02e2af20
......@@ -26,9 +26,7 @@ was a rather big abstraction leak.
This framework aims at solve these problems. It also introduces DT
representation for consumer devices to go get the data they require (MAC
Addresses, SoC/Revision ID, part numbers, and so on) from the NVMEMs. This
framework is based on regmap, so that most of the abstraction available in
regmap can be reused, across multiple types of buses.
Addresses, SoC/Revision ID, part numbers, and so on) from the NVMEMs.
NVMEM Providers
+++++++++++++++
......@@ -45,23 +43,21 @@ nvmem_device pointer.
nvmem_unregister(nvmem) is used to unregister a previously registered provider.
For example, a simple qfprom case::
For example, a simple nvram case::
static struct nvmem_config econfig = {
.name = "qfprom",
.owner = THIS_MODULE,
};
static int qfprom_probe(struct platform_device *pdev)
static int brcm_nvram_probe(struct platform_device *pdev)
{
struct nvmem_config config = {
.name = "brcm-nvram",
.reg_read = brcm_nvram_read,
};
...
econfig.dev = &pdev->dev;
nvmem = nvmem_register(&econfig);
...
}
config.dev = &pdev->dev;
config.priv = priv;
config.size = resource_size(res);
It is mandatory that the NVMEM provider has a regmap associated with its
struct device. Failure to do would return error code from nvmem_register().
devm_nvmem_register(&config);
}
Users of board files can define and register nvmem cells using the
nvmem_cell_table struct::
......
Documentation/hwmon/index.rst
View file @ 02e2af20
......@@ -163,6 +163,8 @@ Hardware Monitoring Kernel Drivers
pim4328
pli1209bc
pm6764tr
peci-cputemp
peci-dimmtemp
pmbus
powr1220
pxe1610
......
Documentation/hwmon/peci-cputemp.rst 0 → 100644
View file @ 02e2af20
.. SPDX-License-Identifier: GPL-2.0-only
Kernel driver peci-cputemp
==========================
Supported chips:
One of Intel server CPUs listed below which is connected to a PECI bus.
* Intel Xeon E5/E7 v3 server processors
Intel Xeon E5-14xx v3 family
Intel Xeon E5-24xx v3 family
Intel Xeon E5-16xx v3 family
Intel Xeon E5-26xx v3 family
Intel Xeon E5-46xx v3 family
Intel Xeon E7-48xx v3 family
Intel Xeon E7-88xx v3 family
* Intel Xeon E5/E7 v4 server processors
Intel Xeon E5-16xx v4 family
Intel Xeon E5-26xx v4 family
Intel Xeon E5-46xx v4 family
Intel Xeon E7-48xx v4 family
Intel Xeon E7-88xx v4 family
* Intel Xeon Scalable server processors
Intel Xeon D family
Intel Xeon Bronze family
Intel Xeon Silver family
Intel Xeon Gold family
Intel Xeon Platinum family
Datasheet: Available from http://www.intel.com/design/literature.htm
Author: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Description
-----------
This driver implements a generic PECI hwmon feature which provides Digital
Thermal Sensor (DTS) thermal readings of the CPU package and CPU cores that are
accessible via the processor PECI interface.
All temperature values are given in millidegree Celsius and will be measurable
only when the target CPU is powered on.
Sysfs interface
-------------------
======================= =======================================================
temp1_label "Die"
temp1_input Provides current die temperature of the CPU package.
temp1_max Provides thermal control temperature of the CPU package
which is also known as Tcontrol.
temp1_crit Provides shutdown temperature of the CPU package which
is also known as the maximum processor junction
temperature, Tjmax or Tprochot.
temp1_crit_hyst Provides the hysteresis value from Tcontrol to Tjmax of
the CPU package.
temp2_label "DTS"
temp2_input Provides current temperature of the CPU package scaled
to match DTS thermal profile.
temp2_max Provides thermal control temperature of the CPU package
which is also known as Tcontrol.
temp2_crit Provides shutdown temperature of the CPU package which
is also known as the maximum processor junction
temperature, Tjmax or Tprochot.
temp2_crit_hyst Provides the hysteresis value from Tcontrol to Tjmax of
the CPU package.
temp3_label "Tcontrol"
temp3_input Provides current Tcontrol temperature of the CPU
package which is also known as Fan Temperature target.
Indicates the relative value from thermal monitor trip
temperature at which fans should be engaged.
temp3_crit Provides Tcontrol critical value of the CPU package
which is same to Tjmax.
temp4_label "Tthrottle"
temp4_input Provides current Tthrottle temperature of the CPU
package. Used for throttling temperature. If this value
is allowed and lower than Tjmax - the throttle will
occur and reported at lower than Tjmax.
temp5_label "Tjmax"
temp5_input Provides the maximum junction temperature, Tjmax of the
CPU package.
temp[6-N]_label Provides string "Core X", where X is resolved core
number.
temp[6-N]_input Provides current temperature of each core.
======================= =======================================================
Documentation/hwmon/peci-dimmtemp.rst 0 → 100644
View file @ 02e2af20
.. SPDX-License-Identifier: GPL-2.0
Kernel driver peci-dimmtemp
===========================
Supported chips:
One of Intel server CPUs listed below which is connected to a PECI bus.
* Intel Xeon E5/E7 v3 server processors
Intel Xeon E5-14xx v3 family
Intel Xeon E5-24xx v3 family
Intel Xeon E5-16xx v3 family
Intel Xeon E5-26xx v3 family
Intel Xeon E5-46xx v3 family
Intel Xeon E7-48xx v3 family
Intel Xeon E7-88xx v3 family
* Intel Xeon E5/E7 v4 server processors
Intel Xeon E5-16xx v4 family
Intel Xeon E5-26xx v4 family
Intel Xeon E5-46xx v4 family
Intel Xeon E7-48xx v4 family
Intel Xeon E7-88xx v4 family
* Intel Xeon Scalable server processors
Intel Xeon D family
Intel Xeon Bronze family
Intel Xeon Silver family
Intel Xeon Gold family
Intel Xeon Platinum family
Datasheet: Available from http://www.intel.com/design/literature.htm
Author: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Description
-----------
This driver implements a generic PECI hwmon feature which provides
Temperature sensor on DIMM readings that are accessible via the processor PECI interface.
All temperature values are given in millidegree Celsius and will be measurable
only when the target CPU is powered on.
Sysfs interface
-------------------
======================= =======================================================
temp[N]_label Provides string "DIMM CI", where C is DIMM channel and
I is DIMM index of the populated DIMM.
temp[N]_input Provides current temperature of the populated DIMM.
temp[N]_max Provides thermal control temperature of the DIMM.
temp[N]_crit Provides shutdown temperature of the DIMM.
======================= =======================================================
Note:
DIMM temperature attributes will appear when the client CPU's BIOS
completes memory training and testing.
Documentation/index.rst
View file @ 02e2af20
......@@ -138,6 +138,7 @@ needed).
scheduler/index
mhi/index
tty/index
peci/index
Architecture-agnostic documentation
-----------------------------------
......
Documentation/peci/index.rst 0 → 100644
View file @ 02e2af20
.. SPDX-License-Identifier: GPL-2.0-only
====================
Linux PECI Subsystem
====================
.. toctree::
peci
.. only:: subproject and html
Indices
=======
* :ref:`genindex`
Documentation/peci/peci.rst 0 → 100644
View file @ 02e2af20
.. SPDX-License-Identifier: GPL-2.0-only
========
Overview
========
The Platform Environment Control Interface (PECI) is a communication
interface between Intel processor and management controllers
(e.g. Baseboard Management Controller, BMC).
PECI provides services that allow the management controller to
configure, monitor and debug platform by accessing various registers.
It defines a dedicated command protocol, where the management
controller is acting as a PECI originator and the processor - as
a PECI responder.
PECI can be used in both single processor and multiple-processor based
systems.
NOTE:
Intel PECI specification is not released as a dedicated document,
instead it is a part of External Design Specification (EDS) for given
Intel CPU. External Design Specifications are usually not publicly
available.
PECI Wire
---------
PECI Wire interface uses a single wire for self-clocking and data
transfer. It does not require any additional control lines - the
physical layer is a self-clocked one-wire bus signal that begins each
bit with a driven, rising edge from an idle near zero volts. The
duration of the signal driven high allows to determine whether the bit
value is logic '0' or logic '1'. PECI Wire also includes variable data
rate established with every message.
For PECI Wire, each processor package will utilize unique, fixed
addresses within a defined range and that address should
have a fixed relationship with the processor socket ID - if one of the
processors is removed, it does not affect addresses of remaining
processors.
PECI subsystem internals
------------------------
.. kernel-doc:: include/linux/peci.h
.. kernel-doc:: drivers/peci/internal.h
.. kernel-doc:: drivers/peci/core.c
.. kernel-doc:: drivers/peci/request.c
PECI CPU Driver API
-------------------
.. kernel-doc:: drivers/peci/cpu.c
MAINTAINERS
View file @ 02e2af20
This diff is collapsed.
arch/arm/boot/dts/aspeed-g4.dtsi
View file @ 02e2af20
......@@ -392,6 +392,17 @@ uart_routing: uart-routing@9c {
};
};
peci0: peci-controller@1e78b000 {
compatible = "aspeed,ast2400-peci";
reg = <0x1e78b000 0x60>;
interrupts = <15>;
clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
resets = <&syscon ASPEED_RESET_PECI>;
cmd-timeout-ms = <1000>;
clock-frequency = <1000000>;
status = "disabled";
};
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
......
arch/arm/boot/dts/aspeed-g5.dtsi
View file @ 02e2af20
......@@ -516,6 +516,17 @@ ibt: ibt@140 {
};
};
peci0: peci-controller@1e78b000 {
compatible = "aspeed,ast2500-peci";
reg = <0x1e78b000 0x60>;
interrupts = <15>;
clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
resets = <&syscon ASPEED_RESET_PECI>;
cmd-timeout-ms = <1000>;
clock-frequency = <1000000>;
status = "disabled";
};
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
......
arch/arm/boot/dts/aspeed-g6.dtsi
View file @ 02e2af20
......@@ -512,6 +512,17 @@ wdt4: watchdog@1e7850c0 {
status = "disabled";
};
peci0: peci-controller@1e78b000 {
compatible = "aspeed,ast2600-peci";
reg = <0x1e78b000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>;
resets = <&syscon ASPEED_RESET_PECI>;
cmd-timeout-ms = <1000>;
clock-frequency = <1000000>;
status = "disabled";
};
lpc: lpc@1e789000 {
compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
......
arch/arm64/Kconfig
View file @ 02e2af20
......@@ -811,7 +811,7 @@ config ARM64_ERRATUM_2224489
config ARM64_ERRATUM_2064142
bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
depends on CORESIGHT_TRBE
default y
help
This option adds the workaround for ARM Cortex-A510 erratum 2064142.
......@@ -829,7 +829,7 @@ config ARM64_ERRATUM_2064142
config ARM64_ERRATUM_2038923
bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
depends on CORESIGHT_TRBE
default y
help
This option adds the workaround for ARM Cortex-A510 erratum 2038923.
......@@ -852,7 +852,7 @@ config ARM64_ERRATUM_2038923
config ARM64_ERRATUM_1902691
bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in
depends on CORESIGHT_TRBE
default y
help
This option adds the workaround for ARM Cortex-A510 erratum 1902691.
......
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ 02e2af20
......@@ -1370,6 +1370,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,smd-channels = "fastrpcsmd-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ 02e2af20
......@@ -839,6 +839,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......@@ -889,6 +890,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file @ 02e2af20
......@@ -1871,6 +1871,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "sdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......@@ -3113,6 +3114,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......@@ -3558,6 +3560,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file @ 02e2af20
......@@ -2682,6 +2682,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "sdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......@@ -2747,6 +2748,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......@@ -4480,6 +4482,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file @ 02e2af20
......@@ -2016,6 +2016,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "sdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......@@ -2085,6 +2086,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "cdsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......@@ -2387,6 +2389,7 @@ fastrpc {
compatible = "qcom,fastrpc";
qcom,glink-channels = "fastrpcglink-apps-dsp";
label = "adsp";
qcom,non-secure-domain;
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm64/include/asm/Kbuild
View file @ 02e2af20
......@@ -3,6 +3,7 @@ generic-y += early_ioremap.h
generic-y += mcs_spinlock.h
generic-y += qrwlock.h
generic-y += qspinlock.h
generic-y += parport.h
generic-y += user.h
generated-y += cpucaps.h
arch/csky/include/asm/Kbuild
View file @ 02e2af20
......@@ -4,5 +4,6 @@ generic-y += extable.h
generic-y += gpio.h
generic-y += kvm_para.h
generic-y += qrwlock.h
generic-y += parport.h
generic-y += user.h
generic-y += vmlinux.lds.h
arch/riscv/include/asm/Kbuild
View file @ 02e2af20
......@@ -2,5 +2,6 @@
generic-y += early_ioremap.h
generic-y += flat.h
generic-y += kvm_para.h
generic-y += parport.h
generic-y += user.h
generic-y += vmlinux.lds.h
arch/um/include/asm/Kbuild
View file @ 02e2af20
......@@ -17,6 +17,7 @@ generic-y += mcs_spinlock.h
generic-y += mmiowb.h
generic-y += module.lds.h
generic-y += param.h
generic-y += parport.h
generic-y += percpu.h
generic-y += preempt.h
generic-y += softirq_stack.h
......
arch/xtensa/include/asm/Kbuild
View file @ 02e2af20
......@@ -4,6 +4,7 @@ generic-y += extable.h
generic-y += kvm_para.h
generic-y += mcs_spinlock.h
generic-y += param.h
generic-y += parport.h
generic-y += qrwlock.h
generic-y += qspinlock.h
generic-y += user.h
drivers/Kconfig
View file @ 02e2af20
......@@ -236,4 +236,7 @@ source "drivers/interconnect/Kconfig"
source "drivers/counter/Kconfig"
source "drivers/most/Kconfig"
source "drivers/peci/Kconfig"
endmenu
drivers/Makefile
View file @ 02e2af20
......@@ -187,3 +187,4 @@ obj-$(CONFIG_GNSS) += gnss/
obj-$(CONFIG_INTERCONNECT) += interconnect/
obj-$(CONFIG_COUNTER) += counter/
obj-$(CONFIG_MOST) += most/
obj-$(CONFIG_PECI) += peci/
drivers/accessibility/speakup/speakup_audptr.c
View file @ 02e2af20
......@@ -126,20 +126,22 @@ static void synth_flush(struct spk_synth *synth)
static void synth_version(struct spk_synth *synth)
{
unsigned char test = 0;
char synth_id[40] = "";
unsigned i;
char synth_id[33];
synth->synth_immediate(synth, "\x05[Q]");
synth_id[test] = synth->io_ops->synth_in(synth);
if (synth_id[test] == 'A') {
do {
/* read version string from synth */
synth_id[++test] = synth->io_ops->synth_in(synth);
} while (synth_id[test] != '\n' && test < 32);
synth_id[++test] = 0x00;
synth_id[0] = synth->io_ops->synth_in(synth);
if (synth_id[0] != 'A')
return;
for (i = 1; i < sizeof(synth_id) - 1; i++) {
/* read version string from synth */
synth_id[i] = synth->io_ops->synth_in(synth);
if (synth_id[i] == '\n')
break;
}
if (synth_id[0] == 'A')
pr_info("%s version: %s", synth->long_name, synth_id);
synth_id[i] = '\0';
pr_info("%s version: %s", synth->long_name, synth_id);
}
static int synth_probe(struct spk_synth *synth)
......
drivers/accessibility/speakup/synth.c
View file @ 02e2af20
......@@ -348,7 +348,7 @@ struct var_t synth_time_vars[] = {
{ TRIGGER, .u.n = {NULL, 20, 10, 2000, 0, 0, NULL } },
{ JIFFY, .u.n = {NULL, 50, 20, 200, 0, 0, NULL } },
{ FULL, .u.n = {NULL, 400, 200, 60000, 0, 0, NULL } },
{ FLUSH, .u.n = {NULL, 4000, 100, 4000, 0, 0, NULL } },
{ FLUSH, .u.n = {NULL, 4000, 10, 4000, 0, 0, NULL } },
V_LAST_VAR
};
......
drivers/android/binder_alloc.c
View file @ 02e2af20
......@@ -1049,18 +1049,14 @@ enum lru_status binder_alloc_free_page(struct list_head *item,
static unsigned long
binder_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
{
unsigned long ret = list_lru_count(&binder_alloc_lru);
return ret;
return list_lru_count(&binder_alloc_lru);
}
static unsigned long
binder_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
{
unsigned long ret;
ret = list_lru_walk(&binder_alloc_lru, binder_alloc_free_page,
return list_lru_walk(&binder_alloc_lru, binder_alloc_free_page,
NULL, sc->nr_to_scan);
return ret;
}
static struct shrinker binder_shrinker = {
......
drivers/ata/ahci.h
View file @ 02e2af20
......@@ -240,8 +240,6 @@ enum {
as default lpm_policy */
AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during
suspend/resume */
AHCI_HFLAG_IGN_NOTSUPP_POWER_ON = (1 << 27), /* ignore -EOPNOTSUPP
from phy_power_on() */
AHCI_HFLAG_NO_SXS = (1 << 28), /* SXS not supported */
/* ap->flags bits */
......
drivers/ata/ahci_mvebu.c
View file @ 02e2af20
......@@ -227,7 +227,7 @@ static const struct ahci_mvebu_plat_data ahci_mvebu_armada_380_plat_data = {
static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = {
.plat_config = ahci_mvebu_armada_3700_config,
.flags = AHCI_HFLAG_SUSPEND_PHYS | AHCI_HFLAG_IGN_NOTSUPP_POWER_ON,
.flags = AHCI_HFLAG_SUSPEND_PHYS,
};
static const struct of_device_id ahci_mvebu_of_match[] = {
......
drivers/ata/libahci_platform.c
View file @ 02e2af20
......@@ -59,7 +59,7 @@ int ahci_platform_enable_phys(struct ahci_host_priv *hpriv)
}
rc = phy_power_on(hpriv->phys[i]);
if (rc && !(rc == -EOPNOTSUPP && (hpriv->flags & AHCI_HFLAG_IGN_NOTSUPP_POWER_ON))) {
if (rc) {
phy_exit(hpriv->phys[i]);
goto disable_phys;
}
......
drivers/bus/Makefile
View file @ 02e2af20
......@@ -39,4 +39,4 @@ obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o
obj-$(CONFIG_DA8XX_MSTPRI) += da8xx-mstpri.o
# MHI
obj-$(CONFIG_MHI_BUS) += mhi/
obj-y += mhi/
drivers/bus/mhi/Kconfig
View file @ 02e2af20
......@@ -2,30 +2,7 @@
#
# MHI bus
#
# Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
# Copyright (c) 2021, Linaro Ltd.
#
config MHI_BUS
tristate "Modem Host Interface (MHI) bus"
help
Bus driver for MHI protocol. Modem Host Interface (MHI) is a
communication protocol used by the host processors to control
and communicate with modem devices over a high speed peripheral
bus or shared memory.
config MHI_BUS_DEBUG
bool "Debugfs support for the MHI bus"
depends on MHI_BUS && DEBUG_FS
help
Enable debugfs support for use with the MHI transport. Allows
reading and/or modifying some values within the MHI controller
for debug and test purposes.
config MHI_BUS_PCI_GENERIC
tristate "MHI PCI controller driver"
depends on MHI_BUS
depends on PCI
help
This driver provides MHI PCI controller driver for devices such as
Qualcomm SDX55 based PCIe modems.
source "drivers/bus/mhi/host/Kconfig"
drivers/bus/mhi/Makefile
View file @ 02e2af20
# core layer
obj-y += core/
obj-$(CONFIG_MHI_BUS_PCI_GENERIC) += mhi_pci_generic.o
mhi_pci_generic-y += pci_generic.o
# Host MHI stack
obj-y += host/
drivers/bus/mhi/common.h 0 → 100644
View file @ 02e2af20
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2022, Linaro Ltd.
*
*/
#ifndef _MHI_COMMON_H
#define _MHI_COMMON_H
#include <linux/bitfield.h>
#include <linux/mhi.h>
/* MHI registers */
#define MHIREGLEN 0x00
#define MHIVER 0x08
#define MHICFG 0x10
#define CHDBOFF 0x18
#define ERDBOFF 0x20
#define BHIOFF 0x28
#define BHIEOFF 0x2c
#define DEBUGOFF 0x30
#define MHICTRL 0x38
#define MHISTATUS 0x48
#define CCABAP_LOWER 0x58
#define CCABAP_HIGHER 0x5c
#define ECABAP_LOWER 0x60
#define ECABAP_HIGHER 0x64
#define CRCBAP_LOWER 0x68
#define CRCBAP_HIGHER 0x6c
#define CRDB_LOWER 0x70
#define CRDB_HIGHER 0x74
#define MHICTRLBASE_LOWER 0x80
#define MHICTRLBASE_HIGHER 0x84
#define MHICTRLLIMIT_LOWER 0x88
#define MHICTRLLIMIT_HIGHER 0x8c
#define MHIDATABASE_LOWER 0x98
#define MHIDATABASE_HIGHER 0x9c
#define MHIDATALIMIT_LOWER 0xa0
#define MHIDATALIMIT_HIGHER 0xa4
/* MHI BHI registers */
#define BHI_BHIVERSION_MINOR 0x00
#define BHI_BHIVERSION_MAJOR 0x04
#define BHI_IMGADDR_LOW 0x08
#define BHI_IMGADDR_HIGH 0x0c
#define BHI_IMGSIZE 0x10
#define BHI_RSVD1 0x14
#define BHI_IMGTXDB 0x18
#define BHI_RSVD2 0x1c
#define BHI_INTVEC 0x20
#define BHI_RSVD3 0x24
#define BHI_EXECENV 0x28
#define BHI_STATUS 0x2c
#define BHI_ERRCODE 0x30
#define BHI_ERRDBG1 0x34
#define BHI_ERRDBG2 0x38
#define BHI_ERRDBG3 0x3c
#define BHI_SERIALNU 0x40
#define BHI_SBLANTIROLLVER 0x44
#define BHI_NUMSEG 0x48
#define BHI_MSMHWID(n) (0x4c + (0x4 * (n)))
#define BHI_OEMPKHASH(n) (0x64 + (0x4 * (n)))
#define BHI_RSVD5 0xc4
/* BHI register bits */
#define BHI_TXDB_SEQNUM_BMSK GENMASK(29, 0)
#define BHI_TXDB_SEQNUM_SHFT 0
#define BHI_STATUS_MASK GENMASK(31, 30)
#define BHI_STATUS_ERROR 0x03
#define BHI_STATUS_SUCCESS 0x02
#define BHI_STATUS_RESET 0x00
/* MHI BHIE registers */
#define BHIE_MSMSOCID_OFFS 0x00
#define BHIE_TXVECADDR_LOW_OFFS 0x2c
#define BHIE_TXVECADDR_HIGH_OFFS 0x30
#define BHIE_TXVECSIZE_OFFS 0x34
#define BHIE_TXVECDB_OFFS 0x3c
#define BHIE_TXVECSTATUS_OFFS 0x44
#define BHIE_RXVECADDR_LOW_OFFS 0x60
#define BHIE_RXVECADDR_HIGH_OFFS 0x64
#define BHIE_RXVECSIZE_OFFS 0x68
#define BHIE_RXVECDB_OFFS 0x70
#define BHIE_RXVECSTATUS_OFFS 0x78
/* BHIE register bits */
#define BHIE_TXVECDB_SEQNUM_BMSK GENMASK(29, 0)
#define BHIE_TXVECDB_SEQNUM_SHFT 0
#define BHIE_TXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
#define BHIE_TXVECSTATUS_SEQNUM_SHFT 0
#define BHIE_TXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
#define BHIE_TXVECSTATUS_STATUS_SHFT 30
#define BHIE_TXVECSTATUS_STATUS_RESET 0x00
#define BHIE_TXVECSTATUS_STATUS_XFER_COMPL 0x02
#define BHIE_TXVECSTATUS_STATUS_ERROR 0x03
#define BHIE_RXVECDB_SEQNUM_BMSK GENMASK(29, 0)
#define BHIE_RXVECDB_SEQNUM_SHFT 0
#define BHIE_RXVECSTATUS_SEQNUM_BMSK GENMASK(29, 0)
#define BHIE_RXVECSTATUS_SEQNUM_SHFT 0
#define BHIE_RXVECSTATUS_STATUS_BMSK GENMASK(31, 30)
#define BHIE_RXVECSTATUS_STATUS_SHFT 30
#define BHIE_RXVECSTATUS_STATUS_RESET 0x00
#define BHIE_RXVECSTATUS_STATUS_XFER_COMPL 0x02
#define BHIE_RXVECSTATUS_STATUS_ERROR 0x03
/* MHI register bits */
#define MHICFG_NHWER_MASK GENMASK(31, 24)
#define MHICFG_NER_MASK GENMASK(23, 16)
#define MHICFG_NHWCH_MASK GENMASK(15, 8)
#define MHICFG_NCH_MASK GENMASK(7, 0)
#define MHICTRL_MHISTATE_MASK GENMASK(15, 8)
#define MHICTRL_RESET_MASK BIT(1)
#define MHISTATUS_MHISTATE_MASK GENMASK(15, 8)
#define MHISTATUS_SYSERR_MASK BIT(2)
#define MHISTATUS_READY_MASK BIT(0)
/* Command Ring Element macros */
/* No operation command */
#define MHI_TRE_CMD_NOOP_PTR 0
#define MHI_TRE_CMD_NOOP_DWORD0 0
#define MHI_TRE_CMD_NOOP_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), MHI_CMD_NOP))
/* Channel reset command */
#define MHI_TRE_CMD_RESET_PTR 0
#define MHI_TRE_CMD_RESET_DWORD0 0
#define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
FIELD_PREP(GENMASK(23, 16), \
MHI_CMD_RESET_CHAN))
/* Channel stop command */
#define MHI_TRE_CMD_STOP_PTR 0
#define MHI_TRE_CMD_STOP_DWORD0 0
#define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
FIELD_PREP(GENMASK(23, 16), \
MHI_CMD_STOP_CHAN))
/* Channel start command */
#define MHI_TRE_CMD_START_PTR 0
#define MHI_TRE_CMD_START_DWORD0 0
#define MHI_TRE_CMD_START_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
FIELD_PREP(GENMASK(23, 16), \
MHI_CMD_START_CHAN))
#define MHI_TRE_GET_DWORD(tre, word) le32_to_cpu((tre)->dword[(word)])
#define MHI_TRE_GET_CMD_CHID(tre) FIELD_GET(GENMASK(31, 24), MHI_TRE_GET_DWORD(tre, 1))
#define MHI_TRE_GET_CMD_TYPE(tre) FIELD_GET(GENMASK(23, 16), MHI_TRE_GET_DWORD(tre, 1))
/* Event descriptor macros */
#define MHI_TRE_EV_PTR(ptr) cpu_to_le64(ptr)
#define MHI_TRE_EV_DWORD0(code, len) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code) | \
FIELD_PREP(GENMASK(15, 0), len))
#define MHI_TRE_EV_DWORD1(chid, type) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \
FIELD_PREP(GENMASK(23, 16), type))
#define MHI_TRE_GET_EV_PTR(tre) le64_to_cpu((tre)->ptr)
#define MHI_TRE_GET_EV_CODE(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
#define MHI_TRE_GET_EV_LEN(tre) FIELD_GET(GENMASK(15, 0), (MHI_TRE_GET_DWORD(tre, 0)))
#define MHI_TRE_GET_EV_CHID(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))
#define MHI_TRE_GET_EV_TYPE(tre) FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 1)))
#define MHI_TRE_GET_EV_STATE(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
#define MHI_TRE_GET_EV_EXECENV(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))
#define MHI_TRE_GET_EV_SEQ(tre) MHI_TRE_GET_DWORD(tre, 0)
#define MHI_TRE_GET_EV_TIME(tre) MHI_TRE_GET_EV_PTR(tre)
#define MHI_TRE_GET_EV_COOKIE(tre) lower_32_bits(MHI_TRE_GET_EV_PTR(tre))
#define MHI_TRE_GET_EV_VEID(tre) FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 0)))
#define MHI_TRE_GET_EV_LINKSPEED(tre) FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))
#define MHI_TRE_GET_EV_LINKWIDTH(tre) FIELD_GET(GENMASK(7, 0), (MHI_TRE_GET_DWORD(tre, 0)))
/* Transfer descriptor macros */
#define MHI_TRE_DATA_PTR(ptr) cpu_to_le64(ptr)
#define MHI_TRE_DATA_DWORD0(len) cpu_to_le32(FIELD_PREP(GENMASK(15, 0), len))
#define MHI_TRE_TYPE_TRANSFER 2
#define MHI_TRE_DATA_DWORD1(bei, ieot, ieob, chain) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \
MHI_TRE_TYPE_TRANSFER) | \
FIELD_PREP(BIT(10), bei) | \
FIELD_PREP(BIT(9), ieot) | \
FIELD_PREP(BIT(8), ieob) | \
FIELD_PREP(BIT(0), chain))
/* RSC transfer descriptor macros */
#define MHI_RSCTRE_DATA_PTR(ptr, len) cpu_to_le64(FIELD_PREP(GENMASK(64, 48), len) | ptr)
#define MHI_RSCTRE_DATA_DWORD0(cookie) cpu_to_le32(cookie)
#define MHI_RSCTRE_DATA_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \
MHI_PKT_TYPE_COALESCING))
enum mhi_pkt_type {
MHI_PKT_TYPE_INVALID = 0x0,
MHI_PKT_TYPE_NOOP_CMD = 0x1,
MHI_PKT_TYPE_TRANSFER = 0x2,
MHI_PKT_TYPE_COALESCING = 0x8,
MHI_PKT_TYPE_RESET_CHAN_CMD = 0x10,
MHI_PKT_TYPE_STOP_CHAN_CMD = 0x11,
MHI_PKT_TYPE_START_CHAN_CMD = 0x12,
MHI_PKT_TYPE_STATE_CHANGE_EVENT = 0x20,
MHI_PKT_TYPE_CMD_COMPLETION_EVENT = 0x21,
MHI_PKT_TYPE_TX_EVENT = 0x22,
MHI_PKT_TYPE_RSC_TX_EVENT = 0x28,
MHI_PKT_TYPE_EE_EVENT = 0x40,
MHI_PKT_TYPE_TSYNC_EVENT = 0x48,
MHI_PKT_TYPE_BW_REQ_EVENT = 0x50,
MHI_PKT_TYPE_STALE_EVENT, /* internal event */
};
/* MHI transfer completion events */
enum mhi_ev_ccs {
MHI_EV_CC_INVALID = 0x0,
MHI_EV_CC_SUCCESS = 0x1,
MHI_EV_CC_EOT = 0x2, /* End of transfer event */
MHI_EV_CC_OVERFLOW = 0x3,
MHI_EV_CC_EOB = 0x4, /* End of block event */
MHI_EV_CC_OOB = 0x5, /* Out of block event */
MHI_EV_CC_DB_MODE = 0x6,
MHI_EV_CC_UNDEFINED_ERR = 0x10,
MHI_EV_CC_BAD_TRE = 0x11,
};
/* Channel state */
enum mhi_ch_state {
MHI_CH_STATE_DISABLED,
MHI_CH_STATE_ENABLED,
MHI_CH_STATE_RUNNING,
MHI_CH_STATE_SUSPENDED,
MHI_CH_STATE_STOP,
MHI_CH_STATE_ERROR,
};
enum mhi_cmd_type {
MHI_CMD_NOP = 1,
MHI_CMD_RESET_CHAN = 16,
MHI_CMD_STOP_CHAN = 17,
MHI_CMD_START_CHAN = 18,
};
#define EV_CTX_RESERVED_MASK GENMASK(7, 0)
#define EV_CTX_INTMODC_MASK GENMASK(15, 8)
#define EV_CTX_INTMODT_MASK GENMASK(31, 16)
struct mhi_event_ctxt {
__le32 intmod;
__le32 ertype;
__le32 msivec;
__le64 rbase __packed __aligned(4);
__le64 rlen __packed __aligned(4);
__le64 rp __packed __aligned(4);
__le64 wp __packed __aligned(4);
};
#define CHAN_CTX_CHSTATE_MASK GENMASK(7, 0)
#define CHAN_CTX_BRSTMODE_MASK GENMASK(9, 8)
#define CHAN_CTX_POLLCFG_MASK GENMASK(15, 10)
#define CHAN_CTX_RESERVED_MASK GENMASK(31, 16)
struct mhi_chan_ctxt {
__le32 chcfg;
__le32 chtype;
__le32 erindex;
__le64 rbase __packed __aligned(4);
__le64 rlen __packed __aligned(4);
__le64 rp __packed __aligned(4);
__le64 wp __packed __aligned(4);
};
struct mhi_cmd_ctxt {
__le32 reserved0;
__le32 reserved1;
__le32 reserved2;
__le64 rbase __packed __aligned(4);
__le64 rlen __packed __aligned(4);
__le64 rp __packed __aligned(4);
__le64 wp __packed __aligned(4);
};
struct mhi_ring_element {
__le64 ptr;
__le32 dword[2];
};
static inline const char *mhi_state_str(enum mhi_state state)
{
switch (state) {
case MHI_STATE_RESET:
return "RESET";
case MHI_STATE_READY:
return "READY";
case MHI_STATE_M0:
return "M0";
case MHI_STATE_M1:
return "M1";
case MHI_STATE_M2:
return "M2";
case MHI_STATE_M3:
return "M3";
case MHI_STATE_M3_FAST:
return "M3 FAST";
case MHI_STATE_BHI:
return "BHI";
case MHI_STATE_SYS_ERR:
return "SYS ERROR";
default:
return "Unknown state";
}
};
#endif /* _MHI_COMMON_H */
drivers/bus/mhi/host/Kconfig 0 → 100644
View file @ 02e2af20
# SPDX-License-Identifier: GPL-2.0
#
# MHI bus
#
# Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
#
config MHI_BUS
tristate "Modem Host Interface (MHI) bus"
help
Bus driver for MHI protocol. Modem Host Interface (MHI) is a
communication protocol used by the host processors to control
and communicate with modem devices over a high speed peripheral
bus or shared memory.
config MHI_BUS_DEBUG
bool "Debugfs support for the MHI bus"
depends on MHI_BUS && DEBUG_FS
help
Enable debugfs support for use with the MHI transport. Allows
reading and/or modifying some values within the MHI controller
for debug and test purposes.
config MHI_BUS_PCI_GENERIC
tristate "MHI PCI controller driver"
depends on MHI_BUS
depends on PCI
help
This driver provides MHI PCI controller driver for devices such as
Qualcomm SDX55 based PCIe modems.
drivers/bus/mhi/core/Makefile → drivers/bus/mhi/host/Makefile
View file @ 02e2af20
obj-$(CONFIG_MHI_BUS) += mhi.o
mhi-y := init.o main.o pm.o boot.o
mhi-$(CONFIG_MHI_BUS_DEBUG) += debugfs.o
obj-$(CONFIG_MHI_BUS_PCI_GENERIC) += mhi_pci_generic.o
mhi_pci_generic-y += pci_generic.o
drivers/bus/mhi/core/boot.c → drivers/bus/mhi/host/boot.c
View file @ 02e2af20
......@@ -46,8 +46,7 @@ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl,
sequence_id = MHI_RANDOM_U32_NONZERO(BHIE_RXVECSTATUS_SEQNUM_BMSK);
mhi_write_reg_field(mhi_cntrl, base, BHIE_RXVECDB_OFFS,
BHIE_RXVECDB_SEQNUM_BMSK, BHIE_RXVECDB_SEQNUM_SHFT,
sequence_id);
BHIE_RXVECDB_SEQNUM_BMSK, sequence_id);
dev_dbg(dev, "Address: %p and len: 0x%zx sequence: %u\n",
&mhi_buf->dma_addr, mhi_buf->len, sequence_id);
......@@ -68,7 +67,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl)
dev_dbg(dev, "Entered with pm_state:%s dev_state:%s ee:%s\n",
to_mhi_pm_state_str(mhi_cntrl->pm_state),
TO_MHI_STATE_STR(mhi_cntrl->dev_state),
mhi_state_str(mhi_cntrl->dev_state),
TO_MHI_EXEC_STR(mhi_cntrl->ee));
/*
......@@ -127,9 +126,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl)
while (retry--) {
ret = mhi_read_reg_field(mhi_cntrl, base, BHIE_RXVECSTATUS_OFFS,
BHIE_RXVECSTATUS_STATUS_BMSK,
BHIE_RXVECSTATUS_STATUS_SHFT,
&rx_status);
BHIE_RXVECSTATUS_STATUS_BMSK, &rx_status);
if (ret)
return -EIO;
......@@ -168,7 +165,6 @@ int mhi_download_rddm_image(struct mhi_controller *mhi_cntrl, bool in_panic)
mhi_read_reg_field(mhi_cntrl, base,
BHIE_RXVECSTATUS_OFFS,
BHIE_RXVECSTATUS_STATUS_BMSK,
BHIE_RXVECSTATUS_STATUS_SHFT,
&rx_status) || rx_status,
msecs_to_jiffies(mhi_cntrl->timeout_ms));
......@@ -203,8 +199,7 @@ static int mhi_fw_load_bhie(struct mhi_controller *mhi_cntrl,
mhi_write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS, mhi_buf->len);
mhi_write_reg_field(mhi_cntrl, base, BHIE_TXVECDB_OFFS,
BHIE_TXVECDB_SEQNUM_BMSK, BHIE_TXVECDB_SEQNUM_SHFT,
sequence_id);
BHIE_TXVECDB_SEQNUM_BMSK, sequence_id);
read_unlock_bh(pm_lock);
/* Wait for the image download to complete */
......@@ -213,7 +208,6 @@ static int mhi_fw_load_bhie(struct mhi_controller *mhi_cntrl,
mhi_read_reg_field(mhi_cntrl, base,
BHIE_TXVECSTATUS_OFFS,
BHIE_TXVECSTATUS_STATUS_BMSK,
BHIE_TXVECSTATUS_STATUS_SHFT,
&tx_status) || tx_status,
msecs_to_jiffies(mhi_cntrl->timeout_ms));
if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) ||
......@@ -265,8 +259,7 @@ static int mhi_fw_load_bhi(struct mhi_controller *mhi_cntrl,
ret = wait_event_timeout(mhi_cntrl->state_event,
MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) ||
mhi_read_reg_field(mhi_cntrl, base, BHI_STATUS,
BHI_STATUS_MASK, BHI_STATUS_SHIFT,
&tx_status) || tx_status,
BHI_STATUS_MASK, &tx_status) || tx_status,
msecs_to_jiffies(mhi_cntrl->timeout_ms));
if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
goto invalid_pm_state;
......
drivers/char/bsr.c
View file @ 02e2af20
This diff is collapsed.
drivers/char/hpet.c
View file @ 02e2af20
This diff is collapsed.
drivers/char/virtio_console.c
View file @ 02e2af20
This diff is collapsed.
drivers/char/xilinx_hwicap/fifo_icap.c
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