Commit 03f2abb0 authored by Yann Dirson's avatar Yann Dirson Committed by Alex Deucher

amdgpu: fix some kernel-doc markup

Those are not today pulled by the sphinx doc, but better be ready.
Signed-off-by: default avatarYann Dirson <ydirson@free.fr>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 19cd8c8b
...@@ -551,11 +551,11 @@ void amdgpu_device_wreg(struct amdgpu_device *adev, ...@@ -551,11 +551,11 @@ void amdgpu_device_wreg(struct amdgpu_device *adev,
trace_amdgpu_device_wreg(adev->pdev->device, reg, v); trace_amdgpu_device_wreg(adev->pdev->device, reg, v);
} }
/* /**
* amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range * amdgpu_mm_wreg_mmio_rlc - write register either with mmio or with RLC path if in range
* *
* this function is invoked only the debugfs register access * this function is invoked only the debugfs register access
* */ */
void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
uint32_t reg, uint32_t v) uint32_t reg, uint32_t v)
{ {
...@@ -1101,7 +1101,7 @@ static void amdgpu_device_wb_fini(struct amdgpu_device *adev) ...@@ -1101,7 +1101,7 @@ static void amdgpu_device_wb_fini(struct amdgpu_device *adev)
} }
/** /**
* amdgpu_device_wb_init- Init Writeback driver info and allocate memory * amdgpu_device_wb_init - Init Writeback driver info and allocate memory
* *
* @adev: amdgpu_device pointer * @adev: amdgpu_device pointer
* *
......
...@@ -624,7 +624,7 @@ static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) ...@@ -624,7 +624,7 @@ static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
#endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
/** /**
* dmub_aux_setconfig_reply_callback - Callback for AUX or SET_CONFIG command. * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
* @adev: amdgpu_device pointer * @adev: amdgpu_device pointer
* @notify: dmub notification structure * @notify: dmub notification structure
* *
......
...@@ -50,9 +50,9 @@ ...@@ -50,9 +50,9 @@
#define AMDGPU_DMUB_NOTIFICATION_MAX 5 #define AMDGPU_DMUB_NOTIFICATION_MAX 5
/** /*
* DMUB Async to Sync Mechanism Status * DMUB Async to Sync Mechanism Status
**/ */
#define DMUB_ASYNC_TO_SYNC_ACCESS_FAIL 1 #define DMUB_ASYNC_TO_SYNC_ACCESS_FAIL 1
#define DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT 2 #define DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT 2
#define DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS 3 #define DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS 3
......
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