Commit 044f507d authored by Sivaprakash Murugesan's avatar Sivaprakash Murugesan Committed by Stephen Boyd

clk: qcom: ipq8074: Add correct index for PCIe clocks

The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC,
GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group.

Move them to the gcc clock group.
Reported-by: default avatarkernel test robot <lkp@intel.com>
Signed-off-by: default avatarSivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1594877570-9280-1-git-send-email-sivaprak@codeaurora.org
Fixes: e7fb524c ("dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe")
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent b4297844
...@@ -230,6 +230,9 @@ ...@@ -230,6 +230,9 @@
#define GCC_GP1_CLK 221 #define GCC_GP1_CLK 221
#define GCC_GP2_CLK 222 #define GCC_GP2_CLK 222
#define GCC_GP3_CLK 223 #define GCC_GP3_CLK 223
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
#define GCC_PCIE0_RCHNG_CLK_SRC 225
#define GCC_PCIE0_RCHNG_CLK 226
#define GCC_BLSP1_BCR 0 #define GCC_BLSP1_BCR 0
#define GCC_BLSP1_QUP1_BCR 1 #define GCC_BLSP1_QUP1_BCR 1
...@@ -363,8 +366,5 @@ ...@@ -363,8 +366,5 @@
#define GCC_PCIE1_AHB_ARES 129 #define GCC_PCIE1_AHB_ARES 129
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 132
#define GCC_PCIE0_RCHNG_CLK_SRC 133
#define GCC_PCIE0_RCHNG_CLK 134
#endif #endif
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