Commit 04d80dbe authored by Heyi Guo's avatar Heyi Guo Committed by Marc Zyngier

irqchip/gic-v3-its: Fix access width for gicr_syncr

GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.
Signed-off-by: default avatarHeyi Guo <guoheyi@huawei.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200225090023.28020-1-guoheyi@huawei.com
parent 47beed51
...@@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) ...@@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
static void wait_for_syncr(void __iomem *rdbase) static void wait_for_syncr(void __iomem *rdbase)
{ {
while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
cpu_relax(); cpu_relax();
} }
......
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