Commit 05d72b8d authored by Xiaojie Yuan's avatar Xiaojie Yuan Committed by Alex Deucher

drm/amdgpu/gmc10: add navi14 support

same as navi10
Signed-off-by: default avatarXiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c8ff09bf
...@@ -524,6 +524,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) ...@@ -524,6 +524,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
if (amdgpu_gart_size == -1) { if (amdgpu_gart_size == -1) {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_NAVI10: case CHIP_NAVI10:
case CHIP_NAVI14:
default: default:
adev->gmc.gart_size = 512ULL << 20; adev->gmc.gart_size = 512ULL << 20;
break; break;
...@@ -601,9 +602,10 @@ static int gmc_v10_0_sw_init(void *handle) ...@@ -601,9 +602,10 @@ static int gmc_v10_0_sw_init(void *handle)
adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_NAVI10: case CHIP_NAVI10:
case CHIP_NAVI14:
/* /*
* To fulfill 4-level page support, * To fulfill 4-level page support,
* vm size is 256TB (48bit), maximum size of Navi10, * vm size is 256TB (48bit), maximum size of Navi10/Navi14,
* block size 512 (9bit) * block size 512 (9bit)
*/ */
amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
...@@ -717,6 +719,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -717,6 +719,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_NAVI10: case CHIP_NAVI10:
case CHIP_NAVI14:
break; break;
default: default:
break; break;
......
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