Commit 06fe918e authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pinctrl changes from Linus Walleij:
 "Some of this stuff is hitting arch/arm/* and have been ACKed by the
  ARM SoC folks, or it's device tree bindings pertaining to the specific
  driver.

  These are the bulk pinctrl changes for kernel v3.7:
   - Add subdrivers for the DB8540 and NHK8815 Nomadik-type ASICs,
     provide platform config for the Nomadik.
   - Add a driver for the i.MX35.
   - Add a driver for the BCM2835, an advanced GPIO expander.
   - Various fixes and clean-ups and minor improvements for the core,
     Nomadik, pinctr-single, sirf drivers.
   - Some platform config for the ux500."

* tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (27 commits)
  pinctrl: add bcm2835 driver
  pinctrl: clarify idle vs sleep states
  pinctrl/nomadik: use irq_find_mapping()
  pinctrl: sirf: add lost chained_irq_enter and exit in sirfsoc_gpio_handle_irq
  pinctrl: sirf: initialize the irq_chip pointer of pinctrl_gpio_range
  pinctrl: sirf: fix spinlock deadlock in sirfsoc_gpio_set_input
  pinctrl: sirf: add missing pins to pinctrl list
  pinctrl: sirf: fix a typo in sirfsoc_gpio_probe
  pinctrl: pinctrl-single: add debugfs pin h/w state info
  ARM: ux500: 8500: update I2C sleep states pinctrl
  pinctrl: Fix potential memory leak in pinctrl_register_one_pin()
  ARM: ux500: tidy up pin sleep modes
  ARM: ux500: fix spi2 pin group
  pinctrl: imx: remove duplicated const
  pinctrl: document semantics vs GPIO
  ARM: ux500: 8500: use hsit_a_2 group for HSI
  pinctrl: use kasprintf() in pinmux_request_gpio()
  pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux
  pinctrl/nomadik : add MC1_a_2 pin MC1 function group list
  pinctrl: pinctrl-single: Make sure we do not change bits outside of mask
  ...
parents dff8360a e1b2dc70
Broadcom BCM2835 GPIO (and pinmux) controller
The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
controller, and pinmux/control device.
Required properties:
- compatible: "brcm,bcm2835-gpio"
- reg: Should contain the physical address of the GPIO module's registes.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted)
- interrupts : The interrupt outputs from the controller. One interrupt per
individual bank followed by the "all banks" interrupt.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells : Should be 2.
The first cell is the GPIO number.
The second cell is used to specify flags:
bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
Valid combinations are 1, 2, 3, 4, 8.
Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Each pin configuration node lists the pin(s) to which it applies, and one or
more of the mux function to select on those pin(s), and pull-up/down
configuration. Each subnode only affects those parameters that are explicitly
listed. In other words, a subnode that lists only a mux function implies no
information about any pull configuration. Similarly, a subnode that lists only
a pul parameter implies no information about the mux function.
Required subnode-properties:
- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
Optional subnode-properties:
- brcm,function: Integer, containing the function to mux to the pin(s):
0: GPIO in
1: GPIO out
2: alt5
3: alt4
4: alt0
5: alt1
6: alt2
7: alt3
- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s):
0: none
1: down
2: up
Each of brcm,function and brcm,pull may contain either a single value which
will be applied to all pins in brcm,pins, or 1 value for each entry in
brcm,pins.
Example:
gpio: gpio {
compatible = "brcm,bcm2835-gpio";
reg = <0x2200000 0xb4>;
interrupts = <2 17>, <2 19>, <2 18>, <2 20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
...@@ -14,10 +14,12 @@ Optional properties: ...@@ -14,10 +14,12 @@ Optional properties:
- pinctrl-single,function-off : function off mode for disabled state if - pinctrl-single,function-off : function off mode for disabled state if
available and same for all registers; if not specified, disabling of available and same for all registers; if not specified, disabling of
pin functions is ignored pin functions is ignored
- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
more than one pin
This driver assumes that there is only one register for each pin, This driver assumes that there is only one register for each pin (unless the
and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
document in this directory. specified in the pinctrl-bindings.txt document in this directory.
The pin configuration nodes for pinctrl-single are specified as pinctrl The pin configuration nodes for pinctrl-single are specified as pinctrl
register offset and value pairs using pinctrl-single,pins. Only the bits register offset and value pairs using pinctrl-single,pins. Only the bits
...@@ -31,6 +33,15 @@ device pinctrl register, and 0x118 contains the desired value of the ...@@ -31,6 +33,15 @@ device pinctrl register, and 0x118 contains the desired value of the
pinctrl register. See the device example and static board pins example pinctrl register. See the device example and static board pins example
below for more information. below for more information.
In case when one register changes more than one pin's mux the
pinctrl-single,bits need to be used which takes three parameters:
pinctrl-single,bits = <0xdc 0x18, 0xff>;
Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
be used when applying this change to the register.
Example: Example:
/* SoC common file */ /* SoC common file */
...@@ -55,6 +66,15 @@ pmx_wkup: pinmux@4a31e040 { ...@@ -55,6 +66,15 @@ pmx_wkup: pinmux@4a31e040 {
pinctrl-single,function-mask = <0xffff>; pinctrl-single,function-mask = <0xffff>;
}; };
control_devconf0: pinmux@48002274 {
compatible = "pinctrl-single";
reg = <0x48002274 4>; /* Single register */
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x5F>;
};
/* board specific .dts file */ /* board specific .dts file */
...@@ -87,6 +107,21 @@ pmx_wkup: pinmux@4a31e040 { ...@@ -87,6 +107,21 @@ pmx_wkup: pinmux@4a31e040 {
}; };
}; };
&control_devconf0 {
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,bits = <
0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
>;
};
mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
pinctrl-single,bits = <
0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
>;
};
};
&uart2 { &uart2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>; pinctrl-0 = <&uart2_pins>;
......
...@@ -289,6 +289,11 @@ Interaction with the GPIO subsystem ...@@ -289,6 +289,11 @@ Interaction with the GPIO subsystem
The GPIO drivers may want to perform operations of various types on the same The GPIO drivers may want to perform operations of various types on the same
physical pins that are also registered as pin controller pins. physical pins that are also registered as pin controller pins.
First and foremost, the two subsystems can be used as completely orthogonal,
see the section named "pin control requests from drivers" and
"drivers needing both pin control and GPIOs" below for details. But in some
situations a cross-subsystem mapping between pins and GPIOs is needed.
Since the pin controller subsystem have its pinspace local to the pin Since the pin controller subsystem have its pinspace local to the pin
controller we need a mapping so that the pin control subsystem can figure out controller we need a mapping so that the pin control subsystem can figure out
which pin controller handles control of a certain GPIO pin. Since a single which pin controller handles control of a certain GPIO pin. Since a single
...@@ -359,6 +364,7 @@ will get an pin number into its handled number range. Further it is also passed ...@@ -359,6 +364,7 @@ will get an pin number into its handled number range. Further it is also passed
the range ID value, so that the pin controller knows which range it should the range ID value, so that the pin controller knows which range it should
deal with. deal with.
PINMUX interfaces PINMUX interfaces
================= =================
...@@ -960,8 +966,8 @@ all get selected, and they all get enabled and disable simultaneously by the ...@@ -960,8 +966,8 @@ all get selected, and they all get enabled and disable simultaneously by the
pinmux core. pinmux core.
Pinmux requests from drivers Pin control requests from drivers
============================ =================================
Generally it is discouraged to let individual drivers get and enable pin Generally it is discouraged to let individual drivers get and enable pin
control. So if possible, handle the pin control in platform code or some other control. So if possible, handle the pin control in platform code or some other
...@@ -969,6 +975,11 @@ place where you have access to all the affected struct device * pointers. In ...@@ -969,6 +975,11 @@ place where you have access to all the affected struct device * pointers. In
some cases where a driver needs to e.g. switch between different mux mappings some cases where a driver needs to e.g. switch between different mux mappings
at runtime this is not possible. at runtime this is not possible.
A typical case is if a driver needs to switch bias of pins from normal
operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
current in sleep mode.
A driver may request a certain control state to be activated, usually just the A driver may request a certain control state to be activated, usually just the
default state like this: default state like this:
...@@ -1058,6 +1069,51 @@ registered. Thus make sure that the error path in your driver gracefully ...@@ -1058,6 +1069,51 @@ registered. Thus make sure that the error path in your driver gracefully
cleans up and is ready to retry the probing later in the startup process. cleans up and is ready to retry the probing later in the startup process.
Drivers needing both pin control and GPIOs
==========================================
Again, it is discouraged to let drivers lookup and select pin control states
themselves, but again sometimes this is unavoidable.
So say that your driver is fetching its resources like this:
#include <linux/pinctrl/consumer.h>
#include <linux/gpio.h>
struct pinctrl *pinctrl;
int gpio;
pinctrl = devm_pinctrl_get_select_default(&dev);
gpio = devm_gpio_request(&dev, 14, "foo");
Here we first request a certain pin state and then request GPIO 14 to be
used. If you're using the subsystems orthogonally like this, you should
nominally always get your pinctrl handle and select the desired pinctrl
state BEFORE requesting the GPIO. This is a semantic convention to avoid
situations that can be electrically unpleasant, you will certainly want to
mux in and bias pins in a certain way before the GPIO subsystems starts to
deal with them.
The above can be hidden: using pinctrl hogs, the pin control driver may be
setting up the config and muxing for the pins when it is probing,
nevertheless orthogonal to the GPIO subsystem.
But there are also situations where it makes sense for the GPIO subsystem
to communicate directly with with the pinctrl subsystem, using the latter
as a back-end. This is when the GPIO driver may call out to the functions
described in the section "Pin control interaction with the GPIO subsystem"
above. This only involves per-pin multiplexing, and will be completely
hidden behind the gpio_*() function namespace. In this case, the driver
need not interact with the pin control subsystem at all.
If a pin control driver and a GPIO driver is dealing with the same pins
and the use cases involve multiplexing, you MUST implement the pin controller
as a back-end for the GPIO driver like this, unless your hardware design
is such that the GPIO controller can override the pin controller's
multiplexing state through hardware without the need to interact with the
pin control system.
System pin control hogging System pin control hogging
========================== ==========================
......
...@@ -891,6 +891,7 @@ config ARCH_NOMADIK ...@@ -891,6 +891,7 @@ config ARCH_NOMADIK
select COMMON_CLK select COMMON_CLK
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select PINCTRL select PINCTRL
select PINCTRL_STN8815
select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_CACHE_L2X0
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
help help
......
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
#include <linux/mtd/partitions.h> #include <linux/mtd/partitions.h>
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/pinctrl/machine.h>
#include <asm/hardware/vic.h> #include <asm/hardware/vic.h>
#include <asm/sizes.h> #include <asm/sizes.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
...@@ -33,6 +34,7 @@ ...@@ -33,6 +34,7 @@
#include <plat/gpio-nomadik.h> #include <plat/gpio-nomadik.h>
#include <plat/mtu.h> #include <plat/mtu.h>
#include <plat/pincfg.h>
#include <linux/platform_data/mtd-nomadik-nand.h> #include <linux/platform_data/mtd-nomadik-nand.h>
#include <mach/fsmc.h> #include <mach/fsmc.h>
...@@ -290,8 +292,42 @@ static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = { ...@@ -290,8 +292,42 @@ static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
}, },
}; };
static unsigned long out_low[] = { PIN_OUTPUT_LOW };
static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
static struct pinctrl_map __initdata nhk8815_pinmap[] = {
PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
/* Hog in MMC/SD card mux */
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
/* MCCLK */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
/* MCCMD */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
/* MCCMDDIR */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
/* MCDAT3-0 */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
/* MCDAT0DIR */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
/* MCDAT31DIR */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
/* MCMSFBCLK */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
/* CD input GPIO */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
/* CD bias drive */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
};
static void __init nhk8815_platform_init(void) static void __init nhk8815_platform_init(void)
{ {
pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
cpu8815_platform_init(); cpu8815_platform_init();
nhk8815_onenand_init(); nhk8815_onenand_init();
platform_add_devices(nhk8815_platform_devices, platform_add_devices(nhk8815_platform_devices,
......
...@@ -83,6 +83,18 @@ void cpu8815_add_gpios(resource_size_t *base, int num, int irq, ...@@ -83,6 +83,18 @@ void cpu8815_add_gpios(resource_size_t *base, int num, int irq,
} }
} }
static inline void
cpu8815_add_pinctrl(struct device *parent, const char *name)
{
struct platform_device_info pdevinfo = {
.parent = parent,
.name = name,
.id = -1,
};
platform_device_register_full(&pdevinfo);
}
static int __init cpu8815_init(void) static int __init cpu8815_init(void)
{ {
struct nmk_gpio_platform_data pdata = { struct nmk_gpio_platform_data pdata = {
...@@ -91,6 +103,7 @@ static int __init cpu8815_init(void) ...@@ -91,6 +103,7 @@ static int __init cpu8815_init(void)
cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base), cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base),
IRQ_GPIO0, &pdata); IRQ_GPIO0, &pdata);
cpu8815_add_pinctrl(NULL, "pinctrl-stn8815");
amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0); amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0);
amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0); amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0);
return 0; return 0;
......
...@@ -30,16 +30,15 @@ static enum custom_pin_cfg_t pinsfor; ...@@ -30,16 +30,15 @@ static enum custom_pin_cfg_t pinsfor;
#define BIAS(a,b) static unsigned long a[] = { b } #define BIAS(a,b) static unsigned long a[] = { b }
BIAS(pd, PIN_PULL_DOWN); BIAS(pd, PIN_PULL_DOWN);
BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
BIAS(in_nopull, PIN_INPUT_NOPULL); BIAS(in_nopull, PIN_INPUT_NOPULL);
BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE); BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
BIAS(in_pu, PIN_INPUT_PULLUP); BIAS(in_pu, PIN_INPUT_PULLUP);
BIAS(in_pd, PIN_INPUT_PULLDOWN); BIAS(in_pd, PIN_INPUT_PULLDOWN);
BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP); BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW); BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
BIAS(out_hi, PIN_OUTPUT_HIGH); BIAS(out_hi, PIN_OUTPUT_HIGH);
BIAS(out_lo, PIN_OUTPUT_LOW); BIAS(out_lo, PIN_OUTPUT_LOW);
BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE); BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
/* These also force them into GPIO mode */ /* These also force them into GPIO mode */
BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED); BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED); BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
...@@ -48,23 +47,32 @@ BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SL ...@@ -48,23 +47,32 @@ BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SL
BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED); BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
/* Sleep modes */ /* Sleep modes */
BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE); BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE); BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
/* We use these to define hog settings that are always done on boot */ /* We use these to define hog settings that are always done on boot */
#define DB8500_MUX_HOG(group,func) \ #define DB8500_MUX_HOG(group,func) \
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func) PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
#define DB8500_PIN_HOG(pin,conf) \ #define DB8500_PIN_HOG(pin,conf) \
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf) PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
#define DB8500_PIN_SLEEP(pin, conf, dev) \
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
pin, conf)
/* These are default states associated with device and changed runtime */ /* These are default states associated with device and changed runtime */
#define DB8500_MUX(group,func,dev) \ #define DB8500_MUX(group,func,dev) \
PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func) PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
#define DB8500_PIN(pin,conf,dev) \ #define DB8500_PIN(pin,conf,dev) \
PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf) PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
#define DB8500_PIN_SLEEP(pin, conf, dev) \
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
pin, conf)
#define DB8500_PIN_SLEEP(pin,conf,dev) \ #define DB8500_PIN_SLEEP(pin,conf,dev) \
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \ PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
...@@ -134,40 +142,47 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { ...@@ -134,40 +142,47 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */ DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */ DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
/* UART0 sleep state */ /* UART0 sleep state */
DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"), DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"), DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"), DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"), DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
/* MSP1 for ALSA codec */ /* MSP1 for ALSA codec */
DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"), DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"), DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"), DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"), DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"), DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"), DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
/* MSP1 sleep state */ /* MSP1 sleep state */
DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"), DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"), DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"), DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"), DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
/* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */ /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"), DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"), DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
/* Mux in LCD VSI1 and pull it up for MCDE HDMI output */ /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"), DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
/* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */ /* Mux in i2c0 block, default state */
DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"), DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"), /* i2c0 sleep state */
DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"), DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
/* Mux in i2c1 block, default state */
DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"), DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"), /* i2c1 sleep state */
DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"), DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
/* Mux in i2c2 block, default state */
DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"), DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"), /* i2c2 sleep state */
DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"), DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
/* Mux in i2c3 block, default state */
DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"), DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"), /* i2c3 sleep state */
DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"), DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
/* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */ /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
DB8500_MUX("mc0_a_1", "mc0", "sdi0"), DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */ DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
...@@ -219,11 +234,15 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { ...@@ -219,11 +234,15 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"), DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */ DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
/* Mux in SPI2 pins on the "other C1" altfunction */ /* Mux in SPI2 pins on the "other C1" altfunction */
DB8500_MUX("spi2_oc1_1", "spi2", "spi2"), DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */ DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */ DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */ DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */ DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
/* SPI2 sleep state */
DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
}; };
/* /*
...@@ -410,7 +429,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = { ...@@ -410,7 +429,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = {
DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu), DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
/* HSI */ /* HSI */
DB8500_MUX_HOG("hsir_a_1", "hsi"), DB8500_MUX_HOG("hsir_a_1", "hsi"),
DB8500_MUX_HOG("hsit_a_1", "hsi"), DB8500_MUX_HOG("hsit_a_2", "hsi"),
DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */ DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */ DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */ DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
...@@ -418,7 +437,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = { ...@@ -418,7 +437,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = {
DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */ DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */ DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */ DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */ DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
}; };
static struct pinctrl_map __initdata u8500_pinmap[] = { static struct pinctrl_map __initdata u8500_pinmap[] = {
......
...@@ -26,11 +26,24 @@ config DEBUG_PINCTRL ...@@ -26,11 +26,24 @@ config DEBUG_PINCTRL
help help
Say Y here to add some extra checks and diagnostics to PINCTRL calls. Say Y here to add some extra checks and diagnostics to PINCTRL calls.
config PINCTRL_BCM2835
bool
select PINMUX
select PINCONF
config PINCTRL_IMX config PINCTRL_IMX
bool bool
select PINMUX select PINMUX
select PINCONF select PINCONF
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
depends on OF
depends on SOC_IMX35
select PINCTRL_IMX
help
Say Y here to enable the imx35 pinctrl driver
config PINCTRL_IMX51 config PINCTRL_IMX51
bool "IMX51 pinctrl driver" bool "IMX51 pinctrl driver"
depends on OF depends on OF
...@@ -86,10 +99,18 @@ config PINCTRL_NOMADIK ...@@ -86,10 +99,18 @@ config PINCTRL_NOMADIK
select PINMUX select PINMUX
select PINCONF select PINCONF
config PINCTRL_STN8815
bool "STN8815 pin controller driver"
depends on PINCTRL_NOMADIK && ARCH_NOMADIK
config PINCTRL_DB8500 config PINCTRL_DB8500
bool "DB8500 pin controller driver" bool "DB8500 pin controller driver"
depends on PINCTRL_NOMADIK && ARCH_U8500 depends on PINCTRL_NOMADIK && ARCH_U8500
config PINCTRL_DB8540
bool "DB8540 pin controller driver"
depends on PINCTRL_NOMADIK && ARCH_U8500
config PINCTRL_PXA168 config PINCTRL_PXA168
bool "PXA168 pin controller driver" bool "PXA168 pin controller driver"
depends on ARCH_MMP depends on ARCH_MMP
......
...@@ -9,7 +9,9 @@ ifeq ($(CONFIG_OF),y) ...@@ -9,7 +9,9 @@ ifeq ($(CONFIG_OF),y)
obj-$(CONFIG_PINCTRL) += devicetree.o obj-$(CONFIG_PINCTRL) += devicetree.o
endif endif
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
...@@ -19,7 +21,9 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o ...@@ -19,7 +21,9 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
......
...@@ -230,8 +230,10 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, ...@@ -230,8 +230,10 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
pindesc->name = name; pindesc->name = name;
} else { } else {
pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", number); pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", number);
if (pindesc->name == NULL) if (pindesc->name == NULL) {
kfree(pindesc);
return -ENOMEM; return -ENOMEM;
}
pindesc->dynamic_name = true; pindesc->dynamic_name = true;
} }
......
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...@@ -432,7 +432,7 @@ static int __devinit imx_pinctrl_parse_groups(struct device_node *np, ...@@ -432,7 +432,7 @@ static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
{ {
unsigned int pin_func_id; unsigned int pin_func_id;
int ret, size; int ret, size;
const const __be32 *list; const __be32 *list;
int i, j; int i, j;
u32 config; u32 config;
......
This source diff could not be displayed because it is too large. You can view the blob instead.
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...@@ -465,6 +465,8 @@ static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25, ...@@ -465,6 +465,8 @@ static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25,
static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15, static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13, DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,
DB8500_PIN_AH15 }; DB8500_PIN_AH15 };
static const unsigned mc1_a_2_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AJ15,
DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,DB8500_PIN_AH15 };
static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
DB8500_PIN_AH12, DB8500_PIN_AH11 }; DB8500_PIN_AH12, DB8500_PIN_AH11 };
static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10, static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10,
...@@ -641,6 +643,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = { ...@@ -641,6 +643,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
...@@ -768,7 +771,7 @@ DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1", ...@@ -768,7 +771,7 @@ DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */ /* MSP2 can not invert the RX/TX pins but has the optional SCK pin */
DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1"); DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1"); DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1"); DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2", "mc1dir_a_1");
DB8500_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2"); DB8500_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1"); DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
DB8500_FUNC_GROUPS(usb, "usb_a_1"); DB8500_FUNC_GROUPS(usb, "usb_a_1");
......
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...@@ -819,6 +819,7 @@ static struct irq_chip nmk_gpio_irq_chip = { ...@@ -819,6 +819,7 @@ static struct irq_chip nmk_gpio_irq_chip = {
.irq_set_wake = nmk_gpio_irq_set_wake, .irq_set_wake = nmk_gpio_irq_set_wake,
.irq_startup = nmk_gpio_irq_startup, .irq_startup = nmk_gpio_irq_startup,
.irq_shutdown = nmk_gpio_irq_shutdown, .irq_shutdown = nmk_gpio_irq_shutdown,
.flags = IRQCHIP_MASK_ON_SUSPEND,
}; };
static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
...@@ -826,16 +827,14 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, ...@@ -826,16 +827,14 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
{ {
struct nmk_gpio_chip *nmk_chip; struct nmk_gpio_chip *nmk_chip;
struct irq_chip *host_chip = irq_get_chip(irq); struct irq_chip *host_chip = irq_get_chip(irq);
unsigned int first_irq;
chained_irq_enter(host_chip, desc); chained_irq_enter(host_chip, desc);
nmk_chip = irq_get_handler_data(irq); nmk_chip = irq_get_handler_data(irq);
first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
while (status) { while (status) {
int bit = __ffs(status); int bit = __ffs(status);
generic_handle_irq(first_irq + bit); generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
status &= ~BIT(bit); status &= ~BIT(bit);
} }
...@@ -1720,8 +1719,12 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev) ...@@ -1720,8 +1719,12 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
of_match_device(nmk_pinctrl_match, &pdev->dev)->data; of_match_device(nmk_pinctrl_match, &pdev->dev)->data;
/* Poke in other ASIC variants here */ /* Poke in other ASIC variants here */
if (version == PINCTRL_NMK_STN8815)
nmk_pinctrl_stn8815_init(&npct->soc);
if (version == PINCTRL_NMK_DB8500) if (version == PINCTRL_NMK_DB8500)
nmk_pinctrl_db8500_init(&npct->soc); nmk_pinctrl_db8500_init(&npct->soc);
if (version == PINCTRL_NMK_DB8540)
nmk_pinctrl_db8540_init(&npct->soc);
/* /*
* We need all the GPIO drivers to probe FIRST, or we will not be able * We need all the GPIO drivers to probe FIRST, or we will not be able
...@@ -1772,6 +1775,7 @@ static struct platform_driver nmk_gpio_driver = { ...@@ -1772,6 +1775,7 @@ static struct platform_driver nmk_gpio_driver = {
static const struct platform_device_id nmk_pinctrl_id[] = { static const struct platform_device_id nmk_pinctrl_id[] = {
{ "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
{ "pinctrl-db8500", PINCTRL_NMK_DB8500 }, { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
{ "pinctrl-db8540", PINCTRL_NMK_DB8540 },
}; };
static struct platform_driver nmk_pinctrl_driver = { static struct platform_driver nmk_pinctrl_driver = {
......
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
/* Package definitions */ /* Package definitions */
#define PINCTRL_NMK_STN8815 0 #define PINCTRL_NMK_STN8815 0
#define PINCTRL_NMK_DB8500 1 #define PINCTRL_NMK_DB8500 1
#define PINCTRL_NMK_DB8540 2
/** /**
* struct nmk_function - Nomadik pinctrl mux function * struct nmk_function - Nomadik pinctrl mux function
...@@ -61,6 +62,19 @@ struct nmk_pinctrl_soc_data { ...@@ -61,6 +62,19 @@ struct nmk_pinctrl_soc_data {
unsigned ngroups; unsigned ngroups;
}; };
#ifdef CONFIG_PINCTRL_STN8815
void nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc);
#else
static inline void
nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
{
}
#endif
#ifdef CONFIG_PINCTRL_DB8500 #ifdef CONFIG_PINCTRL_DB8500
void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc); void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
...@@ -74,4 +88,17 @@ nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc) ...@@ -74,4 +88,17 @@ nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
#endif #endif
#ifdef CONFIG_PINCTRL_DB8540
void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc);
#else
static inline void
nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
{
}
#endif
#endif /* PINCTRL_PINCTRL_NOMADIK_H */ #endif /* PINCTRL_PINCTRL_NOMADIK_H */
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...@@ -232,14 +232,11 @@ int pinmux_request_gpio(struct pinctrl_dev *pctldev, ...@@ -232,14 +232,11 @@ int pinmux_request_gpio(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, struct pinctrl_gpio_range *range,
unsigned pin, unsigned gpio) unsigned pin, unsigned gpio)
{ {
char gpiostr[16];
const char *owner; const char *owner;
int ret; int ret;
/* Conjure some name stating what chip and pin this is taken by */ /* Conjure some name stating what chip and pin this is taken by */
snprintf(gpiostr, 15, "%s:%d", range->name, gpio); owner = kasprintf(GFP_KERNEL, "%s:%d", range->name, gpio);
owner = kstrdup(gpiostr, GFP_KERNEL);
if (!owner) if (!owner)
return -EINVAL; return -EINVAL;
......
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