Commit 074ac38d authored by Pavan Nikhilesh's avatar Pavan Nikhilesh Committed by Paolo Abeni

octeontx2-af: cn10k: Increase outstanding LMTST transactions

Currently the number of outstanding store transactions issued by AP as
a part of LMTST operation is set to 1 i.e default value.
This patch set to max supported value to increase the performance.
Signed-off-by: default avatarPavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: default avatarGeetha sowjanya <gakula@marvell.com>
Link: https://lore.kernel.org/r/20231205055241.26355-1-gakula@marvell.comSigned-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 021b0c95
...@@ -935,6 +935,9 @@ static int rvu_setup_hw_resources(struct rvu *rvu) ...@@ -935,6 +935,9 @@ static int rvu_setup_hw_resources(struct rvu *rvu)
hw->total_vfs = (cfg >> 20) & 0xFFF; hw->total_vfs = (cfg >> 20) & 0xFFF;
hw->max_vfs_per_pf = (cfg >> 40) & 0xFF; hw->max_vfs_per_pf = (cfg >> 40) & 0xFF;
if (!is_rvu_otx2(rvu))
rvu_apr_block_cn10k_init(rvu);
/* Init NPA LF's bitmap */ /* Init NPA LF's bitmap */
block = &hw->block[BLKADDR_NPA]; block = &hw->block[BLKADDR_NPA];
if (!block->implemented) if (!block->implemented)
......
...@@ -969,6 +969,7 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); ...@@ -969,6 +969,7 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw);
/* CN10K RVU - LMT*/ /* CN10K RVU - LMT*/
void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
void rvu_apr_block_cn10k_init(struct rvu *rvu);
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
void rvu_dbg_init(struct rvu *rvu); void rvu_dbg_init(struct rvu *rvu);
......
...@@ -559,3 +559,12 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw) ...@@ -559,3 +559,12 @@ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw)
cfg |= BIT_ULL(1) | BIT_ULL(2); cfg |= BIT_ULL(1) | BIT_ULL(2);
rvu_write64(rvu, blkaddr, NIX_AF_CFG, cfg); rvu_write64(rvu, blkaddr, NIX_AF_CFG, cfg);
} }
void rvu_apr_block_cn10k_init(struct rvu *rvu)
{
u64 reg;
reg = rvu_read64(rvu, BLKADDR_APR, APR_AF_LMT_CFG);
reg |= FIELD_PREP(LMTST_THROTTLE_MASK, LMTST_WR_PEND_MAX);
rvu_write64(rvu, BLKADDR_APR, APR_AF_LMT_CFG, reg);
}
...@@ -733,5 +733,7 @@ ...@@ -733,5 +733,7 @@
#define APR_LMT_MAP_ENT_DIS_SCH_CMP_SHIFT 23 #define APR_LMT_MAP_ENT_DIS_SCH_CMP_SHIFT 23
#define APR_LMT_MAP_ENT_SCH_ENA_SHIFT 22 #define APR_LMT_MAP_ENT_SCH_ENA_SHIFT 22
#define APR_LMT_MAP_ENT_DIS_LINE_PREF_SHIFT 21 #define APR_LMT_MAP_ENT_DIS_LINE_PREF_SHIFT 21
#define LMTST_THROTTLE_MASK GENMASK_ULL(38, 35)
#define LMTST_WR_PEND_MAX 15
#endif /* RVU_REG_H */ #endif /* RVU_REG_H */
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