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Commit 07e571ea authored by Michael Ellerman's avatar Michael Ellerman
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powerpc/64e: Drop dead BOOK3E_MMU_TLB_STATS code 

This code was merged 11 years ago in commit 13363ab9 ("powerpc:
Add definitions used by exception handling on 64-bit Book3E") but was
never able to be built because CONFIG_BOOK3E_MMU_TLB_STATS never
existed. Remove it.
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200724131728.1643966-4-mpe@ellerman.id.au
parent 8cdcde5f
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Showing with 4 additions and 96 deletions
arch/powerpc/include/asm/exception-64e.h
View file @ 07e571ea
...@@ -66,14 +66,7 @@ ...@@ -66,14 +66,7 @@
#define EX_TLB_SRR0 (10 * 8) #define EX_TLB_SRR0 (10 * 8)
#define EX_TLB_SRR1 (11 * 8) #define EX_TLB_SRR1 (11 * 8)
#define EX_TLB_R7 (12 * 8) #define EX_TLB_R7 (12 * 8)
#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
#define EX_TLB_R8 (13 * 8)
#define EX_TLB_R9 (14 * 8)
#define EX_TLB_LR (15 * 8)
#define EX_TLB_SIZE (16 * 8)
#else
#define EX_TLB_SIZE (13 * 8) #define EX_TLB_SIZE (13 * 8)
#endif
#define START_EXCEPTION(label) \ #define START_EXCEPTION(label) \
.globl exc_##label##_book3e; \ .globl exc_##label##_book3e; \
...@@ -110,8 +103,7 @@ exc_##label##_book3e: ...@@ -110,8 +103,7 @@ exc_##label##_book3e:
std r11,EX_TLB_R12(r12); \ std r11,EX_TLB_R12(r12); \
mtspr SPRN_SPRG_TLB_EXFRAME,r14; \ mtspr SPRN_SPRG_TLB_EXFRAME,r14; \
std r15,EX_TLB_SRR1(r12); \ std r15,EX_TLB_SRR1(r12); \
std r16,EX_TLB_SRR0(r12); \ std r16,EX_TLB_SRR0(r12);
TLB_MISS_PROLOG_STATS
/* And these are the matching epilogs that restores things /* And these are the matching epilogs that restores things
* *
...@@ -143,7 +135,6 @@ exc_##label##_book3e: ...@@ -143,7 +135,6 @@ exc_##label##_book3e:
mtspr SPRN_SRR0,r15; \ mtspr SPRN_SRR0,r15; \
ld r15,EX_TLB_R15(r12); \ ld r15,EX_TLB_R15(r12); \
mtspr SPRN_SRR1,r16; \ mtspr SPRN_SRR1,r16; \
TLB_MISS_RESTORE_STATS \
ld r16,EX_TLB_R16(r12); \ ld r16,EX_TLB_R16(r12); \
ld r12,EX_TLB_R12(r12); \ ld r12,EX_TLB_R12(r12); \
...@@ -158,48 +149,6 @@ exc_##label##_book3e: ...@@ -158,48 +149,6 @@ exc_##label##_book3e:
addi r11,r13,PACA_EXTLB; \ addi r11,r13,PACA_EXTLB; \
TLB_MISS_RESTORE(r11) TLB_MISS_RESTORE(r11)
#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
#define TLB_MISS_PROLOG_STATS \
mflr r10; \
std r8,EX_TLB_R8(r12); \
std r9,EX_TLB_R9(r12); \
std r10,EX_TLB_LR(r12);
#define TLB_MISS_RESTORE_STATS \
ld r16,EX_TLB_LR(r12); \
ld r9,EX_TLB_R9(r12); \
ld r8,EX_TLB_R8(r12); \
mtlr r16;
#define TLB_MISS_STATS_D(name) \
addi r9,r13,MMSTAT_DSTATS+name; \
bl tlb_stat_inc;
#define TLB_MISS_STATS_I(name) \
addi r9,r13,MMSTAT_ISTATS+name; \
bl tlb_stat_inc;
#define TLB_MISS_STATS_X(name) \
ld r8,PACA_EXTLB+EX_TLB_ESR(r13); \
cmpdi cr2,r8,-1; \
beq cr2,61f; \
addi r9,r13,MMSTAT_DSTATS+name; \
b 62f; \
61: addi r9,r13,MMSTAT_ISTATS+name; \
62: bl tlb_stat_inc;
#define TLB_MISS_STATS_SAVE_INFO \
std r14,EX_TLB_ESR(r12); /* save ESR */
#define TLB_MISS_STATS_SAVE_INFO_BOLTED \
std r14,PACA_EXTLB+EX_TLB_ESR(r13); /* save ESR */
#else
#define TLB_MISS_PROLOG_STATS
#define TLB_MISS_RESTORE_STATS
#define TLB_MISS_PROLOG_STATS_BOLTED
#define TLB_MISS_RESTORE_STATS_BOLTED
#define TLB_MISS_STATS_D(name)
#define TLB_MISS_STATS_I(name)
#define TLB_MISS_STATS_X(name)
#define TLB_MISS_STATS_Y(name)
#define TLB_MISS_STATS_SAVE_INFO
#define TLB_MISS_STATS_SAVE_INFO_BOLTED
#endif
#define SET_IVOR(vector_number, vector_offset) \ #define SET_IVOR(vector_number, vector_offset) \
LOAD_REG_ADDR(r3,interrupt_base_book3e);\ LOAD_REG_ADDR(r3,interrupt_base_book3e);\
ori r3,r3,vector_offset@l; \ ori r3,r3,vector_offset@l; \
......
arch/powerpc/mm/nohash/tlb_low_64e.S
View file @ 07e571ea
...@@ -71,7 +71,6 @@ START_BTB_FLUSH_SECTION ...@@ -71,7 +71,6 @@ START_BTB_FLUSH_SECTION
END_BTB_FLUSH_SECTION END_BTB_FLUSH_SECTION
std r7,EX_TLB_R7(r12) std r7,EX_TLB_R7(r12)
#endif #endif
TLB_MISS_PROLOG_STATS
.endm .endm
.macro tlb_epilog_bolted .macro tlb_epilog_bolted
...@@ -85,7 +84,6 @@ END_BTB_FLUSH_SECTION ...@@ -85,7 +84,6 @@ END_BTB_FLUSH_SECTION
mtcr r14 mtcr r14
ld r14,EX_TLB_R14(r12) ld r14,EX_TLB_R14(r12)
ld r15,EX_TLB_R15(r12) ld r15,EX_TLB_R15(r12)
TLB_MISS_RESTORE_STATS
ld r16,EX_TLB_R16(r12) ld r16,EX_TLB_R16(r12)
mfspr r12,SPRN_SPRG_GEN_SCRATCH mfspr r12,SPRN_SPRG_GEN_SCRATCH
.endm .endm
...@@ -128,7 +126,6 @@ END_BTB_FLUSH_SECTION ...@@ -128,7 +126,6 @@ END_BTB_FLUSH_SECTION
ori r10,r10,_PAGE_PRESENT ori r10,r10,_PAGE_PRESENT
oris r11,r10,_PAGE_ACCESSED@h oris r11,r10,_PAGE_ACCESSED@h
TLB_MISS_STATS_SAVE_INFO_BOLTED
bne tlb_miss_kernel_bolted bne tlb_miss_kernel_bolted
tlb_miss_common_bolted: tlb_miss_common_bolted:
...@@ -209,7 +206,6 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV) ...@@ -209,7 +206,6 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
tlbwe tlbwe
tlb_miss_done_bolted: tlb_miss_done_bolted:
TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
tlb_epilog_bolted tlb_epilog_bolted
rfi rfi
...@@ -229,11 +225,9 @@ tlb_miss_fault_bolted: ...@@ -229,11 +225,9 @@ tlb_miss_fault_bolted:
andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX
bne itlb_miss_fault_bolted bne itlb_miss_fault_bolted
dtlb_miss_fault_bolted: dtlb_miss_fault_bolted:
TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
tlb_epilog_bolted tlb_epilog_bolted
b exc_data_storage_book3e b exc_data_storage_book3e
itlb_miss_fault_bolted: itlb_miss_fault_bolted:
TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
tlb_epilog_bolted tlb_epilog_bolted
b exc_instruction_storage_book3e b exc_instruction_storage_book3e
...@@ -243,7 +237,6 @@ itlb_miss_fault_bolted: ...@@ -243,7 +237,6 @@ itlb_miss_fault_bolted:
rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
srdi r15,r16,60 /* get region */ srdi r15,r16,60 /* get region */
TLB_MISS_STATS_SAVE_INFO_BOLTED
bne- itlb_miss_fault_bolted bne- itlb_miss_fault_bolted
li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */ li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
...@@ -276,7 +269,6 @@ itlb_miss_fault_bolted: ...@@ -276,7 +269,6 @@ itlb_miss_fault_bolted:
srdi. r15,r16,60 /* get region */ srdi. r15,r16,60 /* get region */
ori r16,r16,1 ori r16,r16,1
TLB_MISS_STATS_SAVE_INFO_BOLTED
bne tlb_miss_kernel_e6500 /* user/kernel test */ bne tlb_miss_kernel_e6500 /* user/kernel test */
b tlb_miss_common_e6500 b tlb_miss_common_e6500
...@@ -288,7 +280,6 @@ itlb_miss_fault_bolted: ...@@ -288,7 +280,6 @@ itlb_miss_fault_bolted:
srdi. r15,r16,60 /* get region */ srdi. r15,r16,60 /* get region */
rldicr r16,r16,0,62 rldicr r16,r16,0,62
TLB_MISS_STATS_SAVE_INFO_BOLTED
bne tlb_miss_kernel_e6500 /* user vs kernel check */ bne tlb_miss_kernel_e6500 /* user vs kernel check */
/* /*
...@@ -460,7 +451,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_SMT) ...@@ -460,7 +451,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_SMT)
.endm .endm
tlb_unlock_e6500 tlb_unlock_e6500
TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
tlb_epilog_bolted tlb_epilog_bolted
rfi rfi
...@@ -519,11 +509,9 @@ tlb_miss_fault_e6500: ...@@ -519,11 +509,9 @@ tlb_miss_fault_e6500:
andi. r16,r16,1 andi. r16,r16,1
bne itlb_miss_fault_e6500 bne itlb_miss_fault_e6500
dtlb_miss_fault_e6500: dtlb_miss_fault_e6500:
TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
tlb_epilog_bolted tlb_epilog_bolted
b exc_data_storage_book3e b exc_data_storage_book3e
itlb_miss_fault_e6500: itlb_miss_fault_e6500:
TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
tlb_epilog_bolted tlb_epilog_bolted
b exc_instruction_storage_book3e b exc_instruction_storage_book3e
#endif /* CONFIG_PPC_FSL_BOOK3E */ #endif /* CONFIG_PPC_FSL_BOOK3E */
...@@ -548,7 +536,6 @@ itlb_miss_fault_e6500: ...@@ -548,7 +536,6 @@ itlb_miss_fault_e6500:
mfspr r16,SPRN_DEAR /* get faulting address */ mfspr r16,SPRN_DEAR /* get faulting address */
srdi r15,r16,60 /* get region */ srdi r15,r16,60 /* get region */
cmpldi cr0,r15,0xc /* linear mapping ? */ cmpldi cr0,r15,0xc /* linear mapping ? */
TLB_MISS_STATS_SAVE_INFO
beq tlb_load_linear /* yes -> go to linear map load */ beq tlb_load_linear /* yes -> go to linear map load */
/* The page tables are mapped virtually linear. At this point, though, /* The page tables are mapped virtually linear. At this point, though,
...@@ -600,7 +587,6 @@ itlb_miss_fault_e6500: ...@@ -600,7 +587,6 @@ itlb_miss_fault_e6500:
/* We got a crappy address, just fault with whatever DEAR and ESR /* We got a crappy address, just fault with whatever DEAR and ESR
* are here * are here
*/ */
TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
TLB_MISS_EPILOG_ERROR TLB_MISS_EPILOG_ERROR
b exc_data_storage_book3e b exc_data_storage_book3e
...@@ -624,7 +610,6 @@ itlb_miss_fault_e6500: ...@@ -624,7 +610,6 @@ itlb_miss_fault_e6500:
*/ */
srdi r15,r16,60 /* get region */ srdi r15,r16,60 /* get region */
cmpldi cr0,r15,0xc /* linear mapping ? */ cmpldi cr0,r15,0xc /* linear mapping ? */
TLB_MISS_STATS_SAVE_INFO
beq tlb_load_linear /* yes -> go to linear map load */ beq tlb_load_linear /* yes -> go to linear map load */
/* We do the user/kernel test for the PID here along with the RW test /* We do the user/kernel test for the PID here along with the RW test
...@@ -646,7 +631,6 @@ itlb_miss_fault_e6500: ...@@ -646,7 +631,6 @@ itlb_miss_fault_e6500:
beq+ normal_tlb_miss beq+ normal_tlb_miss
/* We got a crappy address, just fault */ /* We got a crappy address, just fault */
TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
TLB_MISS_EPILOG_ERROR TLB_MISS_EPILOG_ERROR
b exc_instruction_storage_book3e b exc_instruction_storage_book3e
...@@ -745,7 +729,6 @@ normal_tlb_miss_done: ...@@ -745,7 +729,6 @@ normal_tlb_miss_done:
* level 0 and just going back to userland. They are only needed * level 0 and just going back to userland. They are only needed
* if you are going to take an access fault * if you are going to take an access fault
*/ */
TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
TLB_MISS_EPILOG_SUCCESS TLB_MISS_EPILOG_SUCCESS
rfi rfi
...@@ -757,11 +740,9 @@ normal_tlb_miss_access_fault: ...@@ -757,11 +740,9 @@ normal_tlb_miss_access_fault:
ld r15,EX_TLB_ESR(r12) ld r15,EX_TLB_ESR(r12)
mtspr SPRN_DEAR,r14 mtspr SPRN_DEAR,r14
mtspr SPRN_ESR,r15 mtspr SPRN_ESR,r15
TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
TLB_MISS_EPILOG_ERROR TLB_MISS_EPILOG_ERROR
b exc_data_storage_book3e b exc_data_storage_book3e
1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT) 1: TLB_MISS_EPILOG_ERROR
TLB_MISS_EPILOG_ERROR
b exc_instruction_storage_book3e b exc_instruction_storage_book3e
...@@ -899,7 +880,6 @@ virt_page_table_tlb_miss_done: ...@@ -899,7 +880,6 @@ virt_page_table_tlb_miss_done:
1: 1:
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV) END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
/* Return to caller, normal case */ /* Return to caller, normal case */
TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
TLB_MISS_EPILOG_SUCCESS TLB_MISS_EPILOG_SUCCESS
rfi rfi
...@@ -935,18 +915,15 @@ virt_page_table_tlb_miss_fault: ...@@ -935,18 +915,15 @@ virt_page_table_tlb_miss_fault:
beq 1f beq 1f
mtspr SPRN_DEAR,r15 mtspr SPRN_DEAR,r15
mtspr SPRN_ESR,r16 mtspr SPRN_ESR,r16
TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
TLB_MISS_EPILOG_ERROR TLB_MISS_EPILOG_ERROR
b exc_data_storage_book3e b exc_data_storage_book3e
1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT); 1: TLB_MISS_EPILOG_ERROR
TLB_MISS_EPILOG_ERROR
b exc_instruction_storage_book3e b exc_instruction_storage_book3e
virt_page_table_tlb_miss_whacko_fault: virt_page_table_tlb_miss_whacko_fault:
/* The linear fault will restart everything so ESR and DEAR will /* The linear fault will restart everything so ESR and DEAR will
* not have been clobbered, let's just fault with what we have * not have been clobbered, let's just fault with what we have
*/ */
TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
TLB_MISS_EPILOG_ERROR TLB_MISS_EPILOG_ERROR
b exc_data_storage_book3e b exc_data_storage_book3e
...@@ -971,7 +948,6 @@ virt_page_table_tlb_miss_whacko_fault: ...@@ -971,7 +948,6 @@ virt_page_table_tlb_miss_whacko_fault:
mfspr r16,SPRN_DEAR /* get faulting address */ mfspr r16,SPRN_DEAR /* get faulting address */
srdi r11,r16,60 /* get region */ srdi r11,r16,60 /* get region */
cmpldi cr0,r11,0xc /* linear mapping ? */ cmpldi cr0,r11,0xc /* linear mapping ? */
TLB_MISS_STATS_SAVE_INFO
beq tlb_load_linear /* yes -> go to linear map load */ beq tlb_load_linear /* yes -> go to linear map load */
/* We do the user/kernel test for the PID here along with the RW test /* We do the user/kernel test for the PID here along with the RW test
...@@ -991,7 +967,6 @@ virt_page_table_tlb_miss_whacko_fault: ...@@ -991,7 +967,6 @@ virt_page_table_tlb_miss_whacko_fault:
/* We got a crappy address, just fault with whatever DEAR and ESR /* We got a crappy address, just fault with whatever DEAR and ESR
* are here * are here
*/ */
TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
TLB_MISS_EPILOG_ERROR TLB_MISS_EPILOG_ERROR
b exc_data_storage_book3e b exc_data_storage_book3e
...@@ -1015,7 +990,6 @@ virt_page_table_tlb_miss_whacko_fault: ...@@ -1015,7 +990,6 @@ virt_page_table_tlb_miss_whacko_fault:
*/ */
srdi r11,r16,60 /* get region */ srdi r11,r16,60 /* get region */
cmpldi cr0,r11,0xc /* linear mapping ? */ cmpldi cr0,r11,0xc /* linear mapping ? */
TLB_MISS_STATS_SAVE_INFO
beq tlb_load_linear /* yes -> go to linear map load */ beq tlb_load_linear /* yes -> go to linear map load */
/* We do the user/kernel test for the PID here along with the RW test /* We do the user/kernel test for the PID here along with the RW test
...@@ -1033,7 +1007,6 @@ virt_page_table_tlb_miss_whacko_fault: ...@@ -1033,7 +1007,6 @@ virt_page_table_tlb_miss_whacko_fault:
beq+ htw_tlb_miss beq+ htw_tlb_miss
/* We got a crappy address, just fault */ /* We got a crappy address, just fault */
TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
TLB_MISS_EPILOG_ERROR TLB_MISS_EPILOG_ERROR
b exc_instruction_storage_book3e b exc_instruction_storage_book3e
...@@ -1130,7 +1103,6 @@ htw_tlb_miss_done: ...@@ -1130,7 +1103,6 @@ htw_tlb_miss_done:
* level 0 and just going back to userland. They are only needed * level 0 and just going back to userland. They are only needed
* if you are going to take an access fault * if you are going to take an access fault
*/ */
TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
TLB_MISS_EPILOG_SUCCESS TLB_MISS_EPILOG_SUCCESS
rfi rfi
...@@ -1142,11 +1114,9 @@ htw_tlb_miss_fault: ...@@ -1142,11 +1114,9 @@ htw_tlb_miss_fault:
beq 1f beq 1f
mtspr SPRN_DEAR,r16 mtspr SPRN_DEAR,r16
mtspr SPRN_ESR,r14 mtspr SPRN_ESR,r14
TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
TLB_MISS_EPILOG_ERROR TLB_MISS_EPILOG_ERROR
b exc_data_storage_book3e b exc_data_storage_book3e
1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT) 1: TLB_MISS_EPILOG_ERROR
TLB_MISS_EPILOG_ERROR
b exc_instruction_storage_book3e b exc_instruction_storage_book3e
/* /*
...@@ -1221,7 +1191,6 @@ tlb_load_linear_done: ...@@ -1221,7 +1191,6 @@ tlb_load_linear_done:
* We do that because we can't resume a fault within a TLB * We do that because we can't resume a fault within a TLB
* miss handler, due to MAS and TLB reservation being clobbered. * miss handler, due to MAS and TLB reservation being clobbered.
*/ */
TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
TLB_MISS_EPILOG_ERROR TLB_MISS_EPILOG_ERROR
rfi rfi
...@@ -1233,13 +1202,3 @@ tlb_load_linear_fault: ...@@ -1233,13 +1202,3 @@ tlb_load_linear_fault:
b exc_data_storage_book3e b exc_data_storage_book3e
1: TLB_MISS_EPILOG_ERROR_SPECIAL 1: TLB_MISS_EPILOG_ERROR_SPECIAL
b exc_instruction_storage_book3e b exc_instruction_storage_book3e
#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
.tlb_stat_inc:
1: ldarx r8,0,r9
addi r8,r8,1
stdcx. r8,0,r9
bne- 1b
blr
#endif
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