Commit 094304be authored by Tvrtko Ursulin's avatar Tvrtko Ursulin

drm/i915: Verify GT workaround state after GPU init

Since we now have all the GT workarounds in a table, by adding a simple
shared helper function we can now verify that their values are still
applied after some interesting events in the lifetime of the driver.

Initially we only do this after GPU initialization.

v2:
 Chris Wilson:
 * Simplify verification by realizing it's a simple xor and and.
 * Remove verification from engine reset path.
 * Return bool straight away from the verify API.

v3:
 * API rename. (Chris Wilson)
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20181203125014.3219-4-tvrtko.ursulin@linux.intel.com
parent 4a15c75c
...@@ -53,6 +53,7 @@ ...@@ -53,6 +53,7 @@
#include "i915_vgpu.h" #include "i915_vgpu.h"
#include "intel_drv.h" #include "intel_drv.h"
#include "intel_uc.h" #include "intel_uc.h"
#include "intel_workarounds.h"
static struct drm_driver driver; static struct drm_driver driver;
......
...@@ -5300,7 +5300,10 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) ...@@ -5300,7 +5300,10 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
/* Apply the GT workarounds... */
intel_gt_apply_workarounds(dev_priv); intel_gt_apply_workarounds(dev_priv);
/* ...and determine whether they are sticking. */
intel_gt_verify_workarounds(dev_priv, "init");
i915_gem_init_swizzling(dev_priv); i915_gem_init_swizzling(dev_priv);
......
...@@ -977,6 +977,40 @@ void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv) ...@@ -977,6 +977,40 @@ void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv)
wa_list_apply(dev_priv, &dev_priv->gt_wa_list); wa_list_apply(dev_priv, &dev_priv->gt_wa_list);
} }
static bool
wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from)
{
if ((cur ^ wa->val) & wa->mask) {
DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x, mask=%x)\n",
name, from, i915_mmio_reg_offset(wa->reg), cur,
cur & wa->mask, wa->val, wa->mask);
return false;
}
return true;
}
static bool wa_list_verify(struct drm_i915_private *dev_priv,
const struct i915_wa_list *wal,
const char *from)
{
struct i915_wa *wa;
unsigned int i;
bool ok = true;
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
ok &= wa_verify(wa, I915_READ(wa->reg), wal->name, from);
return ok;
}
bool intel_gt_verify_workarounds(struct drm_i915_private *dev_priv,
const char *from)
{
return wa_list_verify(dev_priv, &dev_priv->gt_wa_list, from);
}
struct whitelist { struct whitelist {
i915_reg_t reg[RING_MAX_NONPRIV_SLOTS]; i915_reg_t reg[RING_MAX_NONPRIV_SLOTS];
unsigned int count; unsigned int count;
......
...@@ -32,6 +32,8 @@ int intel_ctx_workarounds_emit(struct i915_request *rq); ...@@ -32,6 +32,8 @@ int intel_ctx_workarounds_emit(struct i915_request *rq);
void intel_gt_init_workarounds(struct drm_i915_private *dev_priv); void intel_gt_init_workarounds(struct drm_i915_private *dev_priv);
void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv); void intel_gt_apply_workarounds(struct drm_i915_private *dev_priv);
bool intel_gt_verify_workarounds(struct drm_i915_private *dev_priv,
const char *from);
void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine); void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
......
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