Commit 09575693 authored by Mike Turquette's avatar Mike Turquette

Merge branch 'clk-rockchip' into clk-next

parents dae7df47 1fe69496
* Rockchip RK3188/RK3066 Clock and Reset Unit
The RK3188/RK3066 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
"rockchip,rk3066a-cru"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
If missing pll rates are not changable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
Similar macros exist for the reset sources in these files.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "xin32k" - rtc clock - optional,
- "xin27m" - 27mhz crystal input on rk3066 - optional,
- "ext_hsadc" - external HSADC clock - optional,
- "ext_cif0" - external camera clock - optional,
- "ext_rmii" - external RMII clock - optional,
- "ext_jtag" - externalJTAG clock - optional
Example: Clock controller node:
cru: cru@20000000 {
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart0: serial@10124000 {
compatible = "snps,dw-apb-uart";
reg = <0x10124000 0x400>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&cru SCLK_UART0>;
};
* Rockchip RK3288 Clock and Reset Unit
The RK3288 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
- compatible: should be "rockchip,rk3288-cru"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
If missing pll rates are not changable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
used in device tree sources. Similar macros exist for the reset sources in
these files.
External clocks:
There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "xin32k" - rtc clock - optional,
- "ext_i2s" - external I2S clock - optional,
- "ext_hsadc" - external HSADC clock - optional,
- "ext_edp_24m" - external display port clock - optional,
- "ext_vip" - external VIP clock - optional,
- "ext_isp" - external ISP clock - optional,
- "ext_jtag" - external JTAG clock - optional
Example: Clock controller node:
cru: cru@20000000 {
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Example: UART controller node that consumes the clock generated by the clock
controller:
uart0: serial@10124000 {
compatible = "snps,dw-apb-uart";
reg = <0x10124000 0x400>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&cru SCLK_UART0>;
};
......@@ -6,6 +6,9 @@ This binding uses the common clock binding[1].
== Gate clocks ==
These bindings are deprecated!
Please use the soc specific CRU bindings instead.
The gate registers form a continuos block which makes the dt node
structure a matter of taste, as either all gates can be put into
one gate clock spanning all registers or they can be divided into
......
......@@ -2,6 +2,7 @@ config ARCH_ROCKCHIP
bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7
select PINCTRL
select PINCTRL_ROCKCHIP
select ARCH_HAS_RESET_CONTROLLER
select ARCH_REQUIRE_GPIOLIB
select ARM_GIC
select CACHE_L2X0
......
......@@ -64,11 +64,56 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
const struct clk_ops *mux_ops = composite->mux_ops;
struct clk_hw *rate_hw = composite->rate_hw;
struct clk_hw *mux_hw = composite->mux_hw;
struct clk *parent;
unsigned long parent_rate;
long tmp_rate, best_rate = 0;
unsigned long rate_diff;
unsigned long best_rate_diff = ULONG_MAX;
int i;
if (rate_hw && rate_ops && rate_ops->determine_rate) {
rate_hw->clk = hw->clk;
return rate_ops->determine_rate(rate_hw, rate, best_parent_rate,
best_parent_p);
} else if (rate_hw && rate_ops && rate_ops->round_rate &&
mux_hw && mux_ops && mux_ops->set_parent) {
*best_parent_p = NULL;
if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) {
*best_parent_p = clk_get_parent(mux_hw->clk);
*best_parent_rate = __clk_get_rate(*best_parent_p);
return rate_ops->round_rate(rate_hw, rate,
best_parent_rate);
}
for (i = 0; i < __clk_get_num_parents(mux_hw->clk); i++) {
parent = clk_get_parent_by_index(mux_hw->clk, i);
if (!parent)
continue;
parent_rate = __clk_get_rate(parent);
tmp_rate = rate_ops->round_rate(rate_hw, rate,
&parent_rate);
if (tmp_rate < 0)
continue;
rate_diff = abs(rate - tmp_rate);
if (!rate_diff || !*best_parent_p
|| best_rate_diff > rate_diff) {
*best_parent_p = parent;
*best_parent_rate = parent_rate;
best_rate_diff = rate_diff;
best_rate = tmp_rate;
}
if (!rate_diff)
return rate;
}
return best_rate;
} else if (mux_hw && mux_ops && mux_ops->determine_rate) {
mux_hw->clk = hw->clk;
return mux_ops->determine_rate(mux_hw, rate, best_parent_rate,
......@@ -162,7 +207,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
clk_composite_ops = &composite->ops;
if (mux_hw && mux_ops) {
if (!mux_ops->get_parent || !mux_ops->set_parent) {
if (!mux_ops->get_parent) {
clk = ERR_PTR(-EINVAL);
goto err;
}
......@@ -170,7 +215,8 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
composite->mux_hw = mux_hw;
composite->mux_ops = mux_ops;
clk_composite_ops->get_parent = clk_composite_get_parent;
clk_composite_ops->set_parent = clk_composite_set_parent;
if (mux_ops->set_parent)
clk_composite_ops->set_parent = clk_composite_set_parent;
if (mux_ops->determine_rate)
clk_composite_ops->determine_rate = clk_composite_determine_rate;
}
......@@ -180,24 +226,27 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
clk = ERR_PTR(-EINVAL);
goto err;
}
clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
/* .round_rate is a prerequisite for .set_rate */
if (rate_ops->round_rate) {
clk_composite_ops->round_rate = clk_composite_round_rate;
if (rate_ops->set_rate) {
clk_composite_ops->set_rate = clk_composite_set_rate;
}
} else {
WARN(rate_ops->set_rate,
"%s: missing round_rate op is required\n",
__func__);
if (rate_ops->determine_rate)
clk_composite_ops->determine_rate =
clk_composite_determine_rate;
else if (rate_ops->round_rate)
clk_composite_ops->round_rate =
clk_composite_round_rate;
/* .set_rate requires either .round_rate or .determine_rate */
if (rate_ops->set_rate) {
if (rate_ops->determine_rate || rate_ops->round_rate)
clk_composite_ops->set_rate =
clk_composite_set_rate;
else
WARN(1, "%s: missing round_rate op is required\n",
__func__);
}
composite->rate_hw = rate_hw;
composite->rate_ops = rate_ops;
clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
if (rate_ops->determine_rate)
clk_composite_ops->determine_rate = clk_composite_determine_rate;
}
if (gate_hw && gate_ops) {
......
......@@ -3,3 +3,9 @@
#
obj-y += clk-rockchip.o
obj-y += clk.o
obj-y += clk-pll.o
obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-y += clk-rk3188.o
obj-y += clk-rk3288.o
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/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* based on
*
* samsung/clk.c
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2013 Linaro Ltd.
* Author: Thomas Abraham <thomas.ab@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include "clk.h"
/**
* Register a clock branch.
* Most clock branches have a form like
*
* src1 --|--\
* |M |--[GATE]-[DIV]-
* src2 --|--/
*
* sometimes without one of those components.
*/
struct clk *rockchip_clk_register_branch(const char *name,
const char **parent_names, u8 num_parents, void __iomem *base,
int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
u8 div_shift, u8 div_width, u8 div_flags,
struct clk_div_table *div_table, int gate_offset,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
{
struct clk *clk;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
*gate_ops = NULL;
if (num_parents > 1) {
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
mux->reg = base + muxdiv_offset;
mux->shift = mux_shift;
mux->mask = BIT(mux_width) - 1;
mux->flags = mux_flags;
mux->lock = lock;
mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
: &clk_mux_ops;
}
if (gate_offset >= 0) {
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
gate->flags = gate_flags;
gate->reg = base + gate_offset;
gate->bit_idx = gate_shift;
gate->lock = lock;
gate_ops = &clk_gate_ops;
}
if (div_width > 0) {
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
return ERR_PTR(-ENOMEM);
div->flags = div_flags;
div->reg = base + muxdiv_offset;
div->shift = div_shift;
div->width = div_width;
div->lock = lock;
div->table = div_table;
div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
? &clk_divider_ro_ops
: &clk_divider_ops;
}
clk = clk_register_composite(NULL, name, parent_names, num_parents,
mux ? &mux->hw : NULL, mux_ops,
div ? &div->hw : NULL, div_ops,
gate ? &gate->hw : NULL, gate_ops,
flags);
return clk;
}
static DEFINE_SPINLOCK(clk_lock);
static struct clk **clk_table;
static void __iomem *reg_base;
static struct clk_onecell_data clk_data;
static struct device_node *cru_node;
static struct regmap *grf;
void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
unsigned long nr_clks)
{
reg_base = base;
cru_node = np;
grf = ERR_PTR(-EPROBE_DEFER);
clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
if (!clk_table)
pr_err("%s: could not allocate clock lookup table\n", __func__);
clk_data.clks = clk_table;
clk_data.clk_num = nr_clks;
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
struct regmap *rockchip_clk_get_grf(void)
{
if (IS_ERR(grf))
grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
return grf;
}
void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
{
if (clk_table && id)
clk_table[id] = clk;
}
void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
unsigned int nr_pll, int grf_lock_offset)
{
struct clk *clk;
int idx;
for (idx = 0; idx < nr_pll; idx++, list++) {
clk = rockchip_clk_register_pll(list->type, list->name,
list->parent_names, list->num_parents,
reg_base, list->con_offset, grf_lock_offset,
list->lock_shift, list->mode_offset,
list->mode_shift, list->rate_table, &clk_lock);
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s\n", __func__,
list->name);
continue;
}
rockchip_clk_add_lookup(clk, list->id);
}
}
void __init rockchip_clk_register_branches(
struct rockchip_clk_branch *list,
unsigned int nr_clk)
{
struct clk *clk = NULL;
unsigned int idx;
unsigned long flags;
for (idx = 0; idx < nr_clk; idx++, list++) {
flags = list->flags;
/* catch simple muxes */
switch (list->branch_type) {
case branch_mux:
clk = clk_register_mux(NULL, list->name,
list->parent_names, list->num_parents,
flags, reg_base + list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags, &clk_lock);
break;
case branch_divider:
if (list->div_table)
clk = clk_register_divider_table(NULL,
list->name, list->parent_names[0],
flags, reg_base + list->muxdiv_offset,
list->div_shift, list->div_width,
list->div_flags, list->div_table,
&clk_lock);
else
clk = clk_register_divider(NULL, list->name,
list->parent_names[0], flags,
reg_base + list->muxdiv_offset,
list->div_shift, list->div_width,
list->div_flags, &clk_lock);
break;
case branch_fraction_divider:
/* unimplemented */
continue;
break;
case branch_gate:
flags |= CLK_SET_RATE_PARENT;
/* keep all gates untouched for now */
flags |= CLK_IGNORE_UNUSED;
clk = clk_register_gate(NULL, list->name,
list->parent_names[0], flags,
reg_base + list->gate_offset,
list->gate_shift, list->gate_flags, &clk_lock);
break;
case branch_composite:
/* keep all gates untouched for now */
flags |= CLK_IGNORE_UNUSED;
clk = rockchip_clk_register_branch(list->name,
list->parent_names, list->num_parents,
reg_base, list->muxdiv_offset, list->mux_shift,
list->mux_width, list->mux_flags,
list->div_shift, list->div_width,
list->div_flags, list->div_table,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, &clk_lock);
break;
}
/* none of the cases above matched */
if (!clk) {
pr_err("%s: unknown clock type %d\n",
__func__, list->branch_type);
continue;
}
if (IS_ERR(clk)) {
pr_err("%s: failed to register clock %s: %ld\n",
__func__, list->name, PTR_ERR(clk));
continue;
}
rockchip_clk_add_lookup(clk, list->id);
}
}
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* based on
*
* samsung/clk.h
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2013 Linaro Ltd.
* Author: Thomas Abraham <thomas.ab@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef CLK_ROCKCHIP_CLK_H
#define CLK_ROCKCHIP_CLK_H
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#define HIWORD_UPDATE(val, mask, shift) \
((val) << (shift) | (mask) << ((shift) + 16))
/* register positions shared by RK2928, RK3066 and RK3188 */
#define RK2928_PLL_CON(x) (x * 0x4)
#define RK2928_MODE_CON 0x40
#define RK2928_CLKSEL_CON(x) (x * 0x4 + 0x44)
#define RK2928_CLKGATE_CON(x) (x * 0x4 + 0xd0)
#define RK2928_GLB_SRST_FST 0x100
#define RK2928_GLB_SRST_SND 0x104
#define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110)
#define RK2928_MISC_CON 0x134
#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3288_MODE_CON 0x50
#define RK3288_CLKSEL_CON(x) (x * 0x4 + 0x60)
#define RK3288_CLKGATE_CON(x) (x * 0x4 + 0x160)
#define RK3288_GLB_SRST_FST 0x1b0
#define RK3288_GLB_SRST_SND 0x1b4
#define RK3288_SOFTRST_CON(x) (x * 0x4 + 0x1b8)
#define RK3288_MISC_CON 0x1e8
enum rockchip_pll_type {
pll_rk3066,
};
#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
{ \
.rate = _rate##U, \
.nr = _nr, \
.nf = _nf, \
.no = _no, \
.bwadj = (_nf >> 1), \
}
struct rockchip_pll_rate_table {
unsigned long rate;
unsigned int nr;
unsigned int nf;
unsigned int no;
unsigned int bwadj;
};
/**
* struct rockchip_pll_clock: information about pll clock
* @id: platform specific id of the clock.
* @name: name of this pll clock.
* @parent_name: name of the parent clock.
* @flags: optional flags for basic clock.
* @con_offset: offset of the register for configuring the PLL.
* @mode_offset: offset of the register for configuring the PLL-mode.
* @mode_shift: offset inside the mode-register for the mode of this pll.
* @lock_shift: offset inside the lock register for the lock status.
* @type: Type of PLL to be registered.
* @rate_table: Table of usable pll rates
*/
struct rockchip_pll_clock {
unsigned int id;
const char *name;
const char **parent_names;
u8 num_parents;
unsigned long flags;
int con_offset;
int mode_offset;
int mode_shift;
int lock_shift;
enum rockchip_pll_type type;
struct rockchip_pll_rate_table *rate_table;
};
#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
_lshift, _rtable) \
{ \
.id = _id, \
.type = _type, \
.name = _name, \
.parent_names = _pnames, \
.num_parents = ARRAY_SIZE(_pnames), \
.flags = CLK_GET_RATE_NOCACHE | _flags, \
.con_offset = _con, \
.mode_offset = _mode, \
.mode_shift = _mshift, \
.lock_shift = _lshift, \
.rate_table = _rtable, \
}
struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
const char *name, const char **parent_names, u8 num_parents,
void __iomem *base, int con_offset, int grf_lock_offset,
int lock_shift, int reg_mode, int mode_shift,
struct rockchip_pll_rate_table *rate_table,
spinlock_t *lock);
#define PNAME(x) static const char *x[] __initconst
enum rockchip_clk_branch_type {
branch_composite,
branch_mux,
branch_divider,
branch_fraction_divider,
branch_gate,
};
struct rockchip_clk_branch {
unsigned int id;
enum rockchip_clk_branch_type branch_type;
const char *name;
const char **parent_names;
u8 num_parents;
unsigned long flags;
int muxdiv_offset;
u8 mux_shift;
u8 mux_width;
u8 mux_flags;
u8 div_shift;
u8 div_width;
u8 div_flags;
struct clk_div_table *div_table;
int gate_offset;
u8 gate_shift;
u8 gate_flags;
};
#define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
df, go, gs, gf) \
{ \
.id = _id, \
.branch_type = branch_composite, \
.name = cname, \
.parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \
.flags = f, \
.muxdiv_offset = mo, \
.mux_shift = ms, \
.mux_width = mw, \
.mux_flags = mf, \
.div_shift = ds, \
.div_width = dw, \
.div_flags = df, \
.gate_offset = go, \
.gate_shift = gs, \
.gate_flags = gf, \
}
#define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
go, gs, gf) \
{ \
.id = _id, \
.branch_type = branch_composite, \
.name = cname, \
.parent_names = (const char *[]){ pname }, \
.num_parents = 1, \
.flags = f, \
.muxdiv_offset = mo, \
.div_shift = ds, \
.div_width = dw, \
.div_flags = df, \
.gate_offset = go, \
.gate_shift = gs, \
.gate_flags = gf, \
}
#define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
df, dt, go, gs, gf) \
{ \
.id = _id, \
.branch_type = branch_composite, \
.name = cname, \
.parent_names = (const char *[]){ pname }, \
.num_parents = 1, \
.flags = f, \
.muxdiv_offset = mo, \
.div_shift = ds, \
.div_width = dw, \
.div_flags = df, \
.div_table = dt, \
.gate_offset = go, \
.gate_shift = gs, \
.gate_flags = gf, \
}
#define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
go, gs, gf) \
{ \
.id = _id, \
.branch_type = branch_composite, \
.name = cname, \
.parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \
.flags = f, \
.muxdiv_offset = mo, \
.mux_shift = ms, \
.mux_width = mw, \
.mux_flags = mf, \
.gate_offset = go, \
.gate_shift = gs, \
.gate_flags = gf, \
}
#define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
ds, dw, df) \
{ \
.id = _id, \
.branch_type = branch_composite, \
.name = cname, \
.parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \
.flags = f, \
.muxdiv_offset = mo, \
.mux_shift = ms, \
.mux_width = mw, \
.mux_flags = mf, \
.div_shift = ds, \
.div_width = dw, \
.div_flags = df, \
.gate_offset = -1, \
}
#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
{ \
.id = _id, \
.branch_type = branch_fraction_divider, \
.name = cname, \
.parent_names = (const char *[]){ pname }, \
.num_parents = 1, \
.flags = f, \
.muxdiv_offset = mo, \
.div_shift = 16, \
.div_width = 16, \
.div_flags = df, \
.gate_offset = go, \
.gate_shift = gs, \
.gate_flags = gf, \
}
#define MUX(_id, cname, pnames, f, o, s, w, mf) \
{ \
.id = _id, \
.branch_type = branch_mux, \
.name = cname, \
.parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \
.flags = f, \
.muxdiv_offset = o, \
.mux_shift = s, \
.mux_width = w, \
.mux_flags = mf, \
.gate_offset = -1, \
}
#define DIV(_id, cname, pname, f, o, s, w, df) \
{ \
.id = _id, \
.branch_type = branch_divider, \
.name = cname, \
.parent_names = (const char *[]){ pname }, \
.num_parents = 1, \
.flags = f, \
.muxdiv_offset = o, \
.div_shift = s, \
.div_width = w, \
.div_flags = df, \
.gate_offset = -1, \
}
#define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
{ \
.id = _id, \
.branch_type = branch_divider, \
.name = cname, \
.parent_names = (const char *[]){ pname }, \
.num_parents = 1, \
.flags = f, \
.muxdiv_offset = o, \
.div_shift = s, \
.div_width = w, \
.div_flags = df, \
.div_table = dt, \
}
#define GATE(_id, cname, pname, f, o, b, gf) \
{ \
.id = _id, \
.branch_type = branch_gate, \
.name = cname, \
.parent_names = (const char *[]){ pname }, \
.num_parents = 1, \
.flags = f, \
.gate_offset = o, \
.gate_shift = b, \
.gate_flags = gf, \
}
void rockchip_clk_init(struct device_node *np, void __iomem *base,
unsigned long nr_clks);
struct regmap *rockchip_clk_get_grf(void);
void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
unsigned int nr_clk);
void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
unsigned int nr_pll, int grf_lock_offset);
#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
#ifdef CONFIG_RESET_CONTROLLER
void rockchip_register_softrst(struct device_node *np,
unsigned int num_regs,
void __iomem *base, u8 flags);
#else
static inline void rockchip_register_softrst(struct device_node *np,
unsigned int num_regs,
void __iomem *base, u8 flags)
{
}
#endif
#endif
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
#include "clk.h"
struct rockchip_softrst {
struct reset_controller_dev rcdev;
void __iomem *reg_base;
int num_regs;
int num_per_reg;
u8 flags;
spinlock_t lock;
};
static int rockchip_softrst_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rockchip_softrst *softrst = container_of(rcdev,
struct rockchip_softrst,
rcdev);
int bank = id / softrst->num_per_reg;
int offset = id % softrst->num_per_reg;
if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
writel(BIT(offset) | (BIT(offset) << 16),
softrst->reg_base + (bank * 4));
} else {
unsigned long flags;
u32 reg;
spin_lock_irqsave(&softrst->lock, flags);
reg = readl(softrst->reg_base + (bank * 4));
writel(reg | BIT(offset), softrst->reg_base + (bank * 4));
spin_unlock_irqrestore(&softrst->lock, flags);
}
return 0;
}
static int rockchip_softrst_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct rockchip_softrst *softrst = container_of(rcdev,
struct rockchip_softrst,
rcdev);
int bank = id / softrst->num_per_reg;
int offset = id % softrst->num_per_reg;
if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
writel((BIT(offset) << 16), softrst->reg_base + (bank * 4));
} else {
unsigned long flags;
u32 reg;
spin_lock_irqsave(&softrst->lock, flags);
reg = readl(softrst->reg_base + (bank * 4));
writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4));
spin_unlock_irqrestore(&softrst->lock, flags);
}
return 0;
}
static struct reset_control_ops rockchip_softrst_ops = {
.assert = rockchip_softrst_assert,
.deassert = rockchip_softrst_deassert,
};
void __init rockchip_register_softrst(struct device_node *np,
unsigned int num_regs,
void __iomem *base, u8 flags)
{
struct rockchip_softrst *softrst;
int ret;
softrst = kzalloc(sizeof(*softrst), GFP_KERNEL);
if (!softrst)
return;
spin_lock_init(&softrst->lock);
softrst->reg_base = base;
softrst->flags = flags;
softrst->num_regs = num_regs;
softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16
: 32;
softrst->rcdev.owner = THIS_MODULE;
softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg;
softrst->rcdev.ops = &rockchip_softrst_ops;
softrst->rcdev.of_node = np;
ret = reset_controller_register(&softrst->rcdev);
if (ret) {
pr_err("%s: could not register reset controller, %d\n",
__func__, ret);
kfree(softrst);
}
};
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/clock/rk3188-cru-common.h>
/* soft-reset indices */
#define SRST_SRST1 0
#define SRST_SRST2 1
#define SRST_L2MEM 18
#define SRST_I2S0 23
#define SRST_I2S1 24
#define SRST_I2S2 25
#define SRST_TIMER2 29
#define SRST_GPIO4 36
#define SRST_GPIO6 38
#define SRST_TSADC 92
#define SRST_HDMI 96
#define SRST_HDMI_APB 97
#define SRST_CIF1 111
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* core clocks from */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_CPLL 3
#define PLL_GPLL 4
#define CORE_PERI 5
#define CORE_L2C 6
/* sclk gates (special clocks) */
#define SCLK_UART0 64
#define SCLK_UART1 65
#define SCLK_UART2 66
#define SCLK_UART3 67
#define SCLK_MAC 68
#define SCLK_SPI0 69
#define SCLK_SPI1 70
#define SCLK_SARADC 71
#define SCLK_SDMMC 72
#define SCLK_SDIO 73
#define SCLK_EMMC 74
#define SCLK_I2S0 75
#define SCLK_I2S1 76
#define SCLK_I2S2 77
#define SCLK_SPDIF 78
#define SCLK_CIF0 79
#define SCLK_CIF1 80
#define SCLK_OTGPHY0 81
#define SCLK_OTGPHY1 82
#define SCLK_HSADC 83
#define SCLK_TIMER0 84
#define SCLK_TIMER1 85
#define SCLK_TIMER2 86
#define SCLK_TIMER3 87
#define SCLK_TIMER4 88
#define SCLK_TIMER5 89
#define SCLK_TIMER6 90
#define SCLK_JTAG 91
#define SCLK_SMC 92
#define DCLK_LCDC0 190
#define DCLK_LCDC1 191
/* aclk gates */
#define ACLK_DMA1 192
#define ACLK_DMA2 193
#define ACLK_GPS 194
#define ACLK_LCDC0 195
#define ACLK_LCDC1 196
#define ACLK_GPU 197
#define ACLK_SMC 198
#define ACLK_CIF 199
#define ACLK_IPP 200
#define ACLK_RGA 201
#define ACLK_CIF0 202
/* pclk gates */
#define PCLK_GRF 320
#define PCLK_PMU 321
#define PCLK_TIMER0 322
#define PCLK_TIMER1 323
#define PCLK_TIMER2 324
#define PCLK_TIMER3 325
#define PCLK_PWM01 326
#define PCLK_PWM23 327
#define PCLK_SPI0 328
#define PCLK_SPI1 329
#define PCLK_SARADC 330
#define PCLK_WDT 331
#define PCLK_UART0 332
#define PCLK_UART1 333
#define PCLK_UART2 334
#define PCLK_UART3 335
#define PCLK_I2C0 336
#define PCLK_I2C1 337
#define PCLK_I2C2 338
#define PCLK_I2C3 339
#define PCLK_I2C4 340
#define PCLK_GPIO0 341
#define PCLK_GPIO1 342
#define PCLK_GPIO2 343
#define PCLK_GPIO3 344
#define PCLK_GPIO4 345
#define PCLK_GPIO6 346
#define PCLK_EFUSE 347
#define PCLK_TZPC 348
#define PCLK_TSADC 349
/* hclk gates */
#define HCLK_SDMMC 448
#define HCLK_SDIO 449
#define HCLK_EMMC 450
#define HCLK_OTG0 451
#define HCLK_EMAC 452
#define HCLK_SPDIF 453
#define HCLK_I2S0 454
#define HCLK_I2S1 455
#define HCLK_I2S2 456
#define HCLK_OTG1 457
#define HCLK_HSIC 458
#define HCLK_HSADC 459
#define HCLK_PIDF 460
#define HCLK_LCDC0 461
#define HCLK_LCDC1 462
#define HCLK_ROM 463
#define HCLK_CIF0 464
#define HCLK_IPP 465
#define HCLK_RGA 466
#define HCLK_NANDC0 467
#define CLK_NR_CLKS (HCLK_NANDC0 + 1)
/* soft-reset indices */
#define SRST_MCORE 2
#define SRST_CORE0 3
#define SRST_CORE1 4
#define SRST_MCORE_DBG 7
#define SRST_CORE0_DBG 8
#define SRST_CORE1_DBG 9
#define SRST_CORE0_WDT 12
#define SRST_CORE1_WDT 13
#define SRST_STRC_SYS 14
#define SRST_L2C 15
#define SRST_CPU_AHB 17
#define SRST_AHB2APB 19
#define SRST_DMA1 20
#define SRST_INTMEM 21
#define SRST_ROM 22
#define SRST_SPDIF 26
#define SRST_TIMER0 27
#define SRST_TIMER1 28
#define SRST_EFUSE 30
#define SRST_GPIO0 32
#define SRST_GPIO1 33
#define SRST_GPIO2 34
#define SRST_GPIO3 35
#define SRST_UART0 39
#define SRST_UART1 40
#define SRST_UART2 41
#define SRST_UART3 42
#define SRST_I2C0 43
#define SRST_I2C1 44
#define SRST_I2C2 45
#define SRST_I2C3 46
#define SRST_I2C4 47
#define SRST_PWM0 48
#define SRST_PWM1 49
#define SRST_DAP_PO 50
#define SRST_DAP 51
#define SRST_DAP_SYS 52
#define SRST_TPIU_ATB 53
#define SRST_PMU_APB 54
#define SRST_GRF 55
#define SRST_PMU 56
#define SRST_PERI_AXI 57
#define SRST_PERI_AHB 58
#define SRST_PERI_APB 59
#define SRST_PERI_NIU 60
#define SRST_CPU_PERI 61
#define SRST_EMEM_PERI 62
#define SRST_USB_PERI 63
#define SRST_DMA2 64
#define SRST_SMC 65
#define SRST_MAC 66
#define SRST_NANC0 68
#define SRST_USBOTG0 69
#define SRST_USBPHY0 70
#define SRST_OTGC0 71
#define SRST_USBOTG1 72
#define SRST_USBPHY1 73
#define SRST_OTGC1 74
#define SRST_HSADC 76
#define SRST_PIDFILTER 77
#define SRST_DDR_MSCH 79
#define SRST_TZPC 80
#define SRST_SDMMC 81
#define SRST_SDIO 82
#define SRST_EMMC 83
#define SRST_SPI0 84
#define SRST_SPI1 85
#define SRST_WDT 86
#define SRST_SARADC 87
#define SRST_DDRPHY 88
#define SRST_DDRPHY_APB 89
#define SRST_DDRCTL 90
#define SRST_DDRCTL_APB 91
#define SRST_DDRPUB 93
#define SRST_VIO0_AXI 98
#define SRST_VIO0_AHB 99
#define SRST_LCDC0_AXI 100
#define SRST_LCDC0_AHB 101
#define SRST_LCDC0_DCLK 102
#define SRST_LCDC1_AXI 103
#define SRST_LCDC1_AHB 104
#define SRST_LCDC1_DCLK 105
#define SRST_IPP_AXI 106
#define SRST_IPP_AHB 107
#define SRST_RGA_AXI 108
#define SRST_RGA_AHB 109
#define SRST_CIF0 110
#define SRST_VCODEC_AXI 112
#define SRST_VCODEC_AHB 113
#define SRST_VIO1_AXI 114
#define SRST_VCODEC_CPU 115
#define SRST_VCODEC_NIU 116
#define SRST_GPU 120
#define SRST_GPU_NIU 122
#define SRST_TFUN_ATB 125
#define SRST_TFUN_APB 126
#define SRST_CTI4_APB 127
#define SRST_TPIU_APB 128
#define SRST_TRACE 129
#define SRST_CORE_DBG 130
#define SRST_DBG_APB 131
#define SRST_CTI0 132
#define SRST_CTI0_APB 133
#define SRST_CTI1 134
#define SRST_CTI1_APB 135
#define SRST_PTM_CORE0 136
#define SRST_PTM_CORE1 137
#define SRST_PTM0 138
#define SRST_PTM0_ATB 139
#define SRST_PTM1 140
#define SRST_PTM1_ATB 141
#define SRST_CTM 142
#define SRST_TS 143
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/clock/rk3188-cru-common.h>
/* soft-reset indices */
#define SRST_PTM_CORE2 0
#define SRST_PTM_CORE3 1
#define SRST_CORE2 5
#define SRST_CORE3 6
#define SRST_CORE2_DBG 10
#define SRST_CORE3_DBG 11
#define SRST_TIMER2 16
#define SRST_TIMER4 23
#define SRST_I2S0 24
#define SRST_TIMER5 25
#define SRST_TIMER3 29
#define SRST_TIMER6 31
#define SRST_PTM3 36
#define SRST_PTM3_ATB 37
#define SRST_GPS 67
#define SRST_HSICPHY 75
#define SRST_TIMER 78
#define SRST_PTM2 92
#define SRST_CORE2_WDT 94
#define SRST_CORE3_WDT 95
#define SRST_PTM2_ATB 111
#define SRST_HSIC 117
#define SRST_CTI2 118
#define SRST_CTI2_APB 119
#define SRST_GPU_BRIDGE 121
#define SRST_CTI3 123
#define SRST_CTI3_APB 124
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_CPLL 3
#define PLL_GPLL 4
#define PLL_NPLL 5
/* sclk gates (special clocks) */
#define SCLK_GPU 64
#define SCLK_SPI0 65
#define SCLK_SPI1 66
#define SCLK_SPI2 67
#define SCLK_SDMMC 68
#define SCLK_SDIO0 69
#define SCLK_SDIO1 70
#define SCLK_EMMC 71
#define SCLK_TSADC 72
#define SCLK_SARADC 73
#define SCLK_PS2C 74
#define SCLK_NANDC0 75
#define SCLK_NANDC1 76
#define SCLK_UART0 77
#define SCLK_UART1 78
#define SCLK_UART2 79
#define SCLK_UART3 80
#define SCLK_UART4 81
#define SCLK_I2S0 82
#define SCLK_SPDIF 83
#define SCLK_SPDIF8CH 84
#define SCLK_TIMER0 85
#define SCLK_TIMER1 86
#define SCLK_TIMER2 87
#define SCLK_TIMER3 88
#define SCLK_TIMER4 89
#define SCLK_TIMER5 90
#define SCLK_TIMER6 91
#define SCLK_HSADC 92
#define SCLK_OTGPHY0 93
#define SCLK_OTGPHY1 94
#define SCLK_OTGPHY2 95
#define SCLK_OTG_ADP 96
#define SCLK_HSICPHY480M 97
#define SCLK_HSICPHY12M 98
#define SCLK_MACREF 99
#define SCLK_LCDC_PWM0 100
#define SCLK_LCDC_PWM1 101
#define SCLK_MAC_RX 102
#define SCLK_MAC_TX 103
#define DCLK_VOP0 190
#define DCLK_VOP1 191
/* aclk gates */
#define ACLK_GPU 192
#define ACLK_DMAC1 193
#define ACLK_DMAC2 194
#define ACLK_MMU 195
#define ACLK_GMAC 196
#define ACLK_VOP0 197
#define ACLK_VOP1 198
#define ACLK_CRYPTO 199
#define ACLK_RGA 200
/* pclk gates */
#define PCLK_GPIO0 320
#define PCLK_GPIO1 321
#define PCLK_GPIO2 322
#define PCLK_GPIO3 323
#define PCLK_GPIO4 324
#define PCLK_GPIO5 325
#define PCLK_GPIO6 326
#define PCLK_GPIO7 327
#define PCLK_GPIO8 328
#define PCLK_GRF 329
#define PCLK_SGRF 330
#define PCLK_PMU 331
#define PCLK_I2C0 332
#define PCLK_I2C1 333
#define PCLK_I2C2 334
#define PCLK_I2C3 335
#define PCLK_I2C4 336
#define PCLK_I2C5 337
#define PCLK_SPI0 338
#define PCLK_SPI1 339
#define PCLK_SPI2 340
#define PCLK_UART0 341
#define PCLK_UART1 342
#define PCLK_UART2 343
#define PCLK_UART3 344
#define PCLK_UART4 345
#define PCLK_TSADC 346
#define PCLK_SARADC 347
#define PCLK_SIM 348
#define PCLK_GMAC 349
#define PCLK_PWM 350
#define PCLK_RKPWM 351
#define PCLK_PS2C 352
#define PCLK_TIMER 353
#define PCLK_TZPC 354
/* hclk gates */
#define HCLK_GPS 448
#define HCLK_OTG0 449
#define HCLK_USBHOST0 450
#define HCLK_USBHOST1 451
#define HCLK_HSIC 452
#define HCLK_NANDC0 453
#define HCLK_NANDC1 454
#define HCLK_TSP 455
#define HCLK_SDMMC 456
#define HCLK_SDIO0 457
#define HCLK_SDIO1 458
#define HCLK_EMMC 459
#define HCLK_HSADC 460
#define HCLK_CRYPTO 461
#define HCLK_I2S0 462
#define HCLK_SPDIF 463
#define HCLK_SPDIF8CH 464
#define HCLK_VOP0 465
#define HCLK_VOP1 466
#define HCLK_ROM 467
#define HCLK_IEP 468
#define HCLK_ISP 469
#define HCLK_RGA 470
#define CLK_NR_CLKS (HCLK_RGA + 1)
/* soft-reset indices */
#define SRST_CORE0 0
#define SRST_CORE1 1
#define SRST_CORE2 2
#define SRST_CORE3 3
#define SRST_CORE0_PO 4
#define SRST_CORE1_PO 5
#define SRST_CORE2_PO 6
#define SRST_CORE3_PO 7
#define SRST_PDCORE_STRSYS 8
#define SRST_PDBUS_STRSYS 9
#define SRST_L2C 10
#define SRST_TOPDBG 11
#define SRST_CORE0_DBG 12
#define SRST_CORE1_DBG 13
#define SRST_CORE2_DBG 14
#define SRST_CORE3_DBG 15
#define SRST_PDBUG_AHB_ARBITOR 16
#define SRST_EFUSE256 17
#define SRST_DMAC1 18
#define SRST_INTMEM 19
#define SRST_ROM 20
#define SRST_SPDIF8CH 21
#define SRST_TIMER 22
#define SRST_I2S0 23
#define SRST_SPDIF 24
#define SRST_TIMER0 25
#define SRST_TIMER1 26
#define SRST_TIMER2 27
#define SRST_TIMER3 28
#define SRST_TIMER4 29
#define SRST_TIMER5 30
#define SRST_EFUSE 31
#define SRST_GPIO0 32
#define SRST_GPIO1 33
#define SRST_GPIO2 34
#define SRST_GPIO3 35
#define SRST_GPIO4 36
#define SRST_GPIO5 37
#define SRST_GPIO6 38
#define SRST_GPIO7 39
#define SRST_GPIO8 40
#define SRST_I2C0 42
#define SRST_I2C1 43
#define SRST_I2C2 44
#define SRST_I2C3 45
#define SRST_I2C4 46
#define SRST_I2C5 47
#define SRST_DWPWM 48
#define SRST_MMC_PERI 49
#define SRST_PERIPH_MMU 50
#define SRST_DAP 51
#define SRST_DAP_SYS 52
#define SRST_TPIU 53
#define SRST_PMU_APB 54
#define SRST_GRF 55
#define SRST_PMU 56
#define SRST_PERIPH_AXI 57
#define SRST_PERIPH_AHB 58
#define SRST_PERIPH_APB 59
#define SRST_PERIPH_NIU 60
#define SRST_PDPERI_AHB_ARBI 61
#define SRST_EMEM 62
#define SRST_USB_PERI 63
#define SRST_DMAC2 64
#define SRST_MAC 66
#define SRST_GPS 67
#define SRST_RKPWM 69
#define SRST_CCP 71
#define SRST_USBHOST0 72
#define SRST_HSIC 73
#define SRST_HSIC_AUX 74
#define SRST_HSIC_PHY 75
#define SRST_HSADC 76
#define SRST_NANDC0 77
#define SRST_NANDC1 78
#define SRST_TZPC 80
#define SRST_SPI0 83
#define SRST_SPI1 84
#define SRST_SPI2 85
#define SRST_SARADC 87
#define SRST_PDALIVE_NIU 88
#define SRST_PDPMU_INTMEM 89
#define SRST_PDPMU_NIU 90
#define SRST_SGRF 91
#define SRST_VIO_ARBI 96
#define SRST_RGA_NIU 97
#define SRST_VIO0_NIU_AXI 98
#define SRST_VIO_NIU_AHB 99
#define SRST_LCDC0_AXI 100
#define SRST_LCDC0_AHB 101
#define SRST_LCDC0_DCLK 102
#define SRST_VIO1_NIU_AXI 103
#define SRST_VIP 104
#define SRST_RGA_CORE 105
#define SRST_IEP_AXI 106
#define SRST_IEP_AHB 107
#define SRST_RGA_AXI 108
#define SRST_RGA_AHB 109
#define SRST_ISP 110
#define SRST_EDP 111
#define SRST_VCODEC_AXI 112
#define SRST_VCODEC_AHB 113
#define SRST_VIO_H2P 114
#define SRST_MIPIDSI0 115
#define SRST_MIPIDSI1 116
#define SRST_MIPICSI 117
#define SRST_LVDS_PHY 118
#define SRST_LVDS_CON 119
#define SRST_GPU 120
#define SRST_HDMI 121
#define SRST_CORE_PVTM 124
#define SRST_GPU_PVTM 125
#define SRST_MMC0 128
#define SRST_SDIO0 129
#define SRST_SDIO1 130
#define SRST_EMMC 131
#define SRST_USBOTG_AHB 132
#define SRST_USBOTG_PHY 133
#define SRST_USBOTG_CON 134
#define SRST_USBHOST0_AHB 135
#define SRST_USBHOST0_PHY 136
#define SRST_USBHOST0_CON 137
#define SRST_USBHOST1_AHB 138
#define SRST_USBHOST1_PHY 139
#define SRST_USBHOST1_CON 140
#define SRST_USB_ADP 141
#define SRST_ACC_EFUSE 142
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