Commit 09b9b2b2 authored by Ulf Hansson's avatar Ulf Hansson Committed by Mike Turquette

clk: ux500: Define smp_twd clock for u8500

The smp_twd clock is based upon a prcmu_rate clock type
for the PRCMU_ARMSS clock.
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 20aee5b6
...@@ -205,12 +205,16 @@ void u8500_clk_init(void) ...@@ -205,12 +205,16 @@ void u8500_clk_init(void)
clk_register_clkdev(clk, "dsilp2", "dsilink.2"); clk_register_clkdev(clk, "dsilp2", "dsilink.2");
clk_register_clkdev(clk, "dsilp2", "mcde"); clk_register_clkdev(clk, "dsilp2", "mcde");
clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS,
CLK_IS_ROOT|CLK_GET_RATE_NOCACHE|
CLK_IGNORE_UNUSED);
clk_register_clkdev(clk, NULL, "smp_twd");
/* /*
* FIXME: Add special handled PRCMU clocks here: * FIXME: Add special handled PRCMU clocks here:
* 1. smp_twd, use PRCMU_ARMSS. * 1. clk_arm, use PRCMU_ARMCLK.
* 2. clk_arm, use PRCMU_ARMCLK. * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
* 3. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. * 3. ab9540_clkout1yuv, see clkout0yuv
* 4. ab9540_clkout1yuv, see clkout0yuv
*/ */
/* PRCC P-clocks */ /* PRCC P-clocks */
......
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