Commit 09e97b6c authored by Lina Iyer's avatar Lina Iyer Committed by Andy Gross

drivers: qcom: rpmh-rsc: clear wait_for_compl after use

The wait_for_compl register ensures the request sequence is maintained
when sending requests from the TCS. Clear the register after sending
active request and during invalidate of the sleep and wake TCS.
Reported-by: default avatarRaju P.L.S.S.S.N <rplsssn@codeaurora.org>
Signed-off-by: default avatarLina Iyer <ilina@codeaurora.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent 137dc584
...@@ -121,6 +121,7 @@ static int tcs_invalidate(struct rsc_drv *drv, int type) ...@@ -121,6 +121,7 @@ static int tcs_invalidate(struct rsc_drv *drv, int type)
return -EAGAIN; return -EAGAIN;
} }
write_tcs_reg_sync(drv, RSC_DRV_CMD_ENABLE, m, 0); write_tcs_reg_sync(drv, RSC_DRV_CMD_ENABLE, m, 0);
write_tcs_reg_sync(drv, RSC_DRV_CMD_WAIT_FOR_CMPL, m, 0);
} }
bitmap_zero(tcs->slots, MAX_TCS_SLOTS); bitmap_zero(tcs->slots, MAX_TCS_SLOTS);
spin_unlock(&tcs->lock); spin_unlock(&tcs->lock);
...@@ -239,6 +240,7 @@ static irqreturn_t tcs_tx_done(int irq, void *p) ...@@ -239,6 +240,7 @@ static irqreturn_t tcs_tx_done(int irq, void *p)
skip: skip:
/* Reclaim the TCS */ /* Reclaim the TCS */
write_tcs_reg(drv, RSC_DRV_CMD_ENABLE, i, 0); write_tcs_reg(drv, RSC_DRV_CMD_ENABLE, i, 0);
write_tcs_reg(drv, RSC_DRV_CMD_WAIT_FOR_CMPL, i, 0);
write_tcs_reg(drv, RSC_DRV_IRQ_CLEAR, 0, BIT(i)); write_tcs_reg(drv, RSC_DRV_IRQ_CLEAR, 0, BIT(i));
spin_lock(&drv->lock); spin_lock(&drv->lock);
clear_bit(i, drv->tcs_in_use); clear_bit(i, drv->tcs_in_use);
......
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