Commit 0aeef07f authored by Paul Fulghum's avatar Paul Fulghum Committed by Linus Torvalds

[PATCH] synclink update

 - Add support for hardware version 2 (universal PCI) of synclink adapter
 - Use mod_timer() function
parent ce65fb43
/* /*
* linux/drivers/char/synclink.c * linux/drivers/char/synclink.c
* *
* $Id: synclink.c,v 4.6 2003/04/21 17:46:54 paulkf Exp $ * $Id: synclink.c,v 4.9 2003/05/06 21:18:51 paulkf Exp $
* *
* Device driver for Microgate SyncLink ISA and PCI * Device driver for Microgate SyncLink ISA and PCI
* high speed multiprotocol serial adapters. * high speed multiprotocol serial adapters.
...@@ -193,6 +193,7 @@ struct mgsl_struct { ...@@ -193,6 +193,7 @@ struct mgsl_struct {
int flags; int flags;
int count; /* count of opens */ int count; /* count of opens */
int line; int line;
int hw_version;
unsigned short close_delay; unsigned short close_delay;
unsigned short closing_wait; /* time to wait before closing */ unsigned short closing_wait; /* time to wait before closing */
...@@ -917,7 +918,7 @@ MODULE_PARM(txdmabufs,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i"); ...@@ -917,7 +918,7 @@ MODULE_PARM(txdmabufs,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
MODULE_PARM(txholdbufs,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i"); MODULE_PARM(txholdbufs,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
static char *driver_name = "SyncLink serial driver"; static char *driver_name = "SyncLink serial driver";
static char *driver_version = "$Revision: 4.6 $"; static char *driver_version = "$Revision: 4.9 $";
static int synclink_init_one (struct pci_dev *dev, static int synclink_init_one (struct pci_dev *dev,
const struct pci_device_id *ent); const struct pci_device_id *ent);
...@@ -925,6 +926,7 @@ static void synclink_remove_one (struct pci_dev *dev); ...@@ -925,6 +926,7 @@ static void synclink_remove_one (struct pci_dev *dev);
static struct pci_device_id synclink_pci_tbl[] __devinitdata = { static struct pci_device_id synclink_pci_tbl[] __devinitdata = {
{ PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, }, { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
{ PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
{ 0, }, /* terminate list */ { 0, }, /* terminate list */
}; };
MODULE_DEVICE_TABLE(pci, synclink_pci_tbl); MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
...@@ -4216,9 +4218,7 @@ int load_next_tx_holding_buffer(struct mgsl_struct *info) ...@@ -4216,9 +4218,7 @@ int load_next_tx_holding_buffer(struct mgsl_struct *info)
info->get_tx_holding_index=0; info->get_tx_holding_index=0;
/* restart transmit timer */ /* restart transmit timer */
del_timer(&info->tx_timer); mod_timer(&info->tx_timer, jiffies + jiffies_from_ms(5000));
info->tx_timer.expires = jiffies + jiffies_from_ms(5000);
add_timer(&info->tx_timer);
ret = 1; ret = 1;
} }
...@@ -4436,12 +4436,12 @@ void mgsl_add_device( struct mgsl_struct *info ) ...@@ -4436,12 +4436,12 @@ void mgsl_add_device( struct mgsl_struct *info )
info->max_frame_size = 65535; info->max_frame_size = 65535;
if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
printk( "SyncLink device %s added:PCI bus IO=%04X IRQ=%d Mem=%08X LCR=%08X MaxFrameSize=%u\n", printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
info->device_name, info->io_base, info->irq_level, info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
info->phys_memory_base, info->phys_lcr_base, info->phys_memory_base, info->phys_lcr_base,
info->max_frame_size ); info->max_frame_size );
} else { } else {
printk( "SyncLink device %s added:ISA bus IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n", printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
info->device_name, info->io_base, info->irq_level, info->dma_level, info->device_name, info->io_base, info->irq_level, info->dma_level,
info->max_frame_size ); info->max_frame_size );
} }
...@@ -5296,10 +5296,11 @@ void usc_set_sdlc_mode( struct mgsl_struct *info ) ...@@ -5296,10 +5296,11 @@ void usc_set_sdlc_mode( struct mgsl_struct *info )
info->mbre_bit = BIT8; info->mbre_bit = BIT8;
outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */ outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
/* Enable DMAEN (Port 7, Bit 14) */ if (info->bus_type == MGSL_BUS_TYPE_ISA) {
/* This connects the DMA request signal to the ISA bus */ /* Enable DMAEN (Port 7, Bit 14) */
/* on the ISA adapter. This has no effect for the PCI adapter */ /* This connects the DMA request signal to the ISA bus */
usc_OutReg( info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14) ); usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
}
/* DMA Control Register (DCR) /* DMA Control Register (DCR)
* *
...@@ -6276,10 +6277,11 @@ void usc_set_async_mode( struct mgsl_struct *info ) ...@@ -6276,10 +6277,11 @@ void usc_set_async_mode( struct mgsl_struct *info )
usc_EnableMasterIrqBit( info ); usc_EnableMasterIrqBit( info );
/* Enable INTEN (Port 6, Bit12) */ if (info->bus_type == MGSL_BUS_TYPE_ISA) {
/* This connects the IRQ request signal to the ISA bus */ /* Enable INTEN (Port 6, Bit12) */
/* on the ISA adapter. This has no effect for the PCI adapter */ /* This connects the IRQ request signal to the ISA bus */
usc_OutReg( info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12) ); usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
}
} /* end of usc_set_async_mode() */ } /* end of usc_set_async_mode() */
...@@ -6370,10 +6372,11 @@ void usc_set_sync_mode( struct mgsl_struct *info ) ...@@ -6370,10 +6372,11 @@ void usc_set_sync_mode( struct mgsl_struct *info )
usc_loopback_frame( info ); usc_loopback_frame( info );
usc_set_sdlc_mode( info ); usc_set_sdlc_mode( info );
/* Enable INTEN (Port 6, Bit12) */ if (info->bus_type == MGSL_BUS_TYPE_ISA) {
/* This connects the IRQ request signal to the ISA bus */ /* Enable INTEN (Port 6, Bit12) */
/* on the ISA adapter. This has no effect for the PCI adapter */ /* This connects the IRQ request signal to the ISA bus */
usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12)); usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
}
usc_enable_aux_clock(info, info->params.clock_speed); usc_enable_aux_clock(info, info->params.clock_speed);
...@@ -8115,17 +8118,20 @@ static int __init synclink_init_one (struct pci_dev *dev, ...@@ -8115,17 +8118,20 @@ static int __init synclink_init_one (struct pci_dev *dev,
info->bus_type = MGSL_BUS_TYPE_PCI; info->bus_type = MGSL_BUS_TYPE_PCI;
info->io_addr_size = 8; info->io_addr_size = 8;
info->irq_flags = SA_SHIRQ; info->irq_flags = SA_SHIRQ;
/* Store the PCI9050 misc control register value because a flaw if (dev->device == 0x0210) {
* in the PCI9050 prevents LCR registers from being read if /* Version 1 PCI9030 based universal PCI adapter */
* BIOS assigns an LCR base address with bit 7 set. info->misc_ctrl_value = 0x007c4080;
* info->hw_version = 1;
* Only the misc control register is accessed for which only } else {
* write access is needed, so set an initial value and change /* Version 0 PCI9050 based 5V PCI adapter
* bits to the device instance data as we write the value * A PCI9050 bug prevents reading LCR registers if
* to the actual misc control register. * LCR base address bit 7 is set. Maintain shadow
*/ * value so we can write to LCR misc control reg.
info->misc_ctrl_value = 0x087e4546; */
info->misc_ctrl_value = 0x087e4546;
info->hw_version = 0;
}
mgsl_add_device(info); mgsl_add_device(info);
......
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