Commit 0b9754e9 authored by Kevin Scott's avatar Kevin Scott Committed by Jeff Kirsher

i40e: Correct mask assignment value

Make mask value of all 1s.  Value of -1 can't be used for u32 type.

Change-ID: I49d58b77639939fe7447a229dbf1f4a1bf7419ce
Signed-off-by: default avatarKevin Scott <kevin.c.scott@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 838d41d9
...@@ -858,7 +858,7 @@ static void i40e_write_dword(u8 *hmc_bits, ...@@ -858,7 +858,7 @@ static void i40e_write_dword(u8 *hmc_bits,
if (ce_info->width < 32) if (ce_info->width < 32)
mask = ((u32)1 << ce_info->width) - 1; mask = ((u32)1 << ce_info->width) - 1;
else else
mask = -1; mask = 0xFFFFFFFF;
/* don't swizzle the bits until after the mask because the mask bits /* don't swizzle the bits until after the mask because the mask bits
* will be in a different bit position on big endian machines * will be in a different bit position on big endian machines
...@@ -910,7 +910,7 @@ static void i40e_write_qword(u8 *hmc_bits, ...@@ -910,7 +910,7 @@ static void i40e_write_qword(u8 *hmc_bits,
if (ce_info->width < 64) if (ce_info->width < 64)
mask = ((u64)1 << ce_info->width) - 1; mask = ((u64)1 << ce_info->width) - 1;
else else
mask = -1; mask = 0xFFFFFFFFFFFFFFFF;
/* don't swizzle the bits until after the mask because the mask bits /* don't swizzle the bits until after the mask because the mask bits
* will be in a different bit position on big endian machines * will be in a different bit position on big endian machines
......
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