Commit 0bc67917 authored by Florian Fainelli's avatar Florian Fainelli Committed by Ralf Baechle

MIPS: AR7: Fix loops per jiffies on TNETD7200 devices

TNETD7200 run their CPU clock faster than the default CPU clock we assume.
In order to have the correct loops per jiffies settings, initialize clocks right
before setting mips_hpt_frequency. As a side effect, we can no longer use
msleep in clocks.c which requires other parts of the kernel to be initialized,
so replace these with mdelay.
Signed-off-by: default avatarFlorian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1749/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ff42d620
...@@ -239,12 +239,12 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock, ...@@ -239,12 +239,12 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
calculate(base_clock, frequency, &prediv, &postdiv, &mul); calculate(base_clock, frequency, &prediv, &postdiv, &mul);
writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl); writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
msleep(1); mdelay(1);
writel(4, &clock->pll); writel(4, &clock->pll);
while (readl(&clock->pll) & PLL_STATUS) while (readl(&clock->pll) & PLL_STATUS)
; ;
writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
msleep(75); mdelay(75);
} }
static void __init tnetd7300_init_clocks(void) static void __init tnetd7300_init_clocks(void)
...@@ -456,7 +456,7 @@ void clk_put(struct clk *clk) ...@@ -456,7 +456,7 @@ void clk_put(struct clk *clk)
} }
EXPORT_SYMBOL(clk_put); EXPORT_SYMBOL(clk_put);
int __init ar7_init_clocks(void) void __init ar7_init_clocks(void)
{ {
switch (ar7_chip_id()) { switch (ar7_chip_id()) {
case AR7_CHIP_7100: case AR7_CHIP_7100:
...@@ -472,7 +472,4 @@ int __init ar7_init_clocks(void) ...@@ -472,7 +472,4 @@ int __init ar7_init_clocks(void)
} }
/* adjust vbus clock rate */ /* adjust vbus clock rate */
vbus_clk.rate = bus_clk.rate / 2; vbus_clk.rate = bus_clk.rate / 2;
return 0;
} }
arch_initcall(ar7_init_clocks);
...@@ -30,6 +30,9 @@ void __init plat_time_init(void) ...@@ -30,6 +30,9 @@ void __init plat_time_init(void)
{ {
struct clk *cpu_clk; struct clk *cpu_clk;
/* Initialize ar7 clocks so the CPU clock frequency is correct */
ar7_init_clocks();
cpu_clk = clk_get(NULL, "cpu"); cpu_clk = clk_get(NULL, "cpu");
if (IS_ERR(cpu_clk)) { if (IS_ERR(cpu_clk)) {
printk(KERN_ERR "unable to get cpu clock\n"); printk(KERN_ERR "unable to get cpu clock\n");
......
...@@ -201,5 +201,6 @@ static inline void ar7_device_off(u32 bit) ...@@ -201,5 +201,6 @@ static inline void ar7_device_off(u32 bit)
} }
int __init ar7_gpio_init(void); int __init ar7_gpio_init(void);
void __init ar7_init_clocks(void);
#endif /* __AR7_H__ */ #endif /* __AR7_H__ */
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