Commit 0cf8ff05 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Mark Brown

ASoC: SOF: add default IPC capability and file paths

This patch adds a default IPC type for each platform, along with file
paths to be used for each IPC type. To make reviews simpler, we only
modify platform descriptors in this table, the information will be
used in the next patch.

The Intel IPCv4 is only supported on Intel platforms after APL, and
not by default. In follow-up patches, support for SKL and KBL will be
added, and in those two cases the IPCv4 will be the default (and only
supported mode).
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@intel.com>
Reviewed-by: default avatarPéter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20220414184817.362215-4-pierre-louis.bossart@linux.intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent a3757915
...@@ -124,6 +124,10 @@ struct sof_dev_desc { ...@@ -124,6 +124,10 @@ struct sof_dev_desc {
/* defaults for no codec mode */ /* defaults for no codec mode */
const char *nocodec_tplg_filename; const char *nocodec_tplg_filename;
/* information on supported IPCs */
unsigned int ipc_supported_mask;
enum sof_ipc_type ipc_default;
/* defaults paths for firmware and topology files */ /* defaults paths for firmware and topology files */
const char *default_fw_path[SOF_IPC_TYPE_COUNT]; const char *default_fw_path[SOF_IPC_TYPE_COUNT];
const char *default_tplg_path[SOF_IPC_TYPE_COUNT]; const char *default_tplg_path[SOF_IPC_TYPE_COUNT];
......
...@@ -54,6 +54,8 @@ static const struct sof_dev_desc renoir_desc = { ...@@ -54,6 +54,8 @@ static const struct sof_dev_desc renoir_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &renoir_chip_info, .chip_info = &renoir_chip_info,
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "amd/sof", [SOF_IPC] = "amd/sof",
}, },
......
...@@ -613,6 +613,8 @@ static const struct snd_sof_dsp_ops sof_imx8x_ops = { ...@@ -613,6 +613,8 @@ static const struct snd_sof_dsp_ops sof_imx8x_ops = {
}; };
static struct sof_dev_desc sof_of_imx8qxp_desc = { static struct sof_dev_desc sof_of_imx8qxp_desc = {
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "imx/sof", [SOF_IPC] = "imx/sof",
}, },
...@@ -625,6 +627,8 @@ static struct sof_dev_desc sof_of_imx8qxp_desc = { ...@@ -625,6 +627,8 @@ static struct sof_dev_desc sof_of_imx8qxp_desc = {
}; };
static struct sof_dev_desc sof_of_imx8qm_desc = { static struct sof_dev_desc sof_of_imx8qm_desc = {
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "imx/sof", [SOF_IPC] = "imx/sof",
}, },
......
...@@ -473,6 +473,8 @@ static const struct snd_sof_dsp_ops sof_imx8m_ops = { ...@@ -473,6 +473,8 @@ static const struct snd_sof_dsp_ops sof_imx8m_ops = {
}; };
static struct sof_dev_desc sof_of_imx8mp_desc = { static struct sof_dev_desc sof_of_imx8mp_desc = {
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "imx/sof", [SOF_IPC] = "imx/sof",
}, },
......
...@@ -646,6 +646,8 @@ static const struct sof_dev_desc sof_acpi_broadwell_desc = { ...@@ -646,6 +646,8 @@ static const struct sof_dev_desc sof_acpi_broadwell_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = 0, .irqindex_host_ipc = 0,
.chip_info = &bdw_chip_info, .chip_info = &bdw_chip_info,
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
}, },
......
...@@ -388,6 +388,8 @@ static const struct sof_dev_desc sof_acpi_baytrailcr_desc = { ...@@ -388,6 +388,8 @@ static const struct sof_dev_desc sof_acpi_baytrailcr_desc = {
.resindex_imr_base = 2, .resindex_imr_base = 2,
.irqindex_host_ipc = 0, .irqindex_host_ipc = 0,
.chip_info = &byt_chip_info, .chip_info = &byt_chip_info,
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
}, },
...@@ -406,6 +408,8 @@ static const struct sof_dev_desc sof_acpi_baytrail_desc = { ...@@ -406,6 +408,8 @@ static const struct sof_dev_desc sof_acpi_baytrail_desc = {
.resindex_imr_base = 2, .resindex_imr_base = 2,
.irqindex_host_ipc = 5, .irqindex_host_ipc = 5,
.chip_info = &byt_chip_info, .chip_info = &byt_chip_info,
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
}, },
...@@ -424,6 +428,8 @@ static const struct sof_dev_desc sof_acpi_cherrytrail_desc = { ...@@ -424,6 +428,8 @@ static const struct sof_dev_desc sof_acpi_cherrytrail_desc = {
.resindex_imr_base = 2, .resindex_imr_base = 2,
.irqindex_host_ipc = 5, .irqindex_host_ipc = 5,
.chip_info = &cht_chip_info, .chip_info = &cht_chip_info,
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
}, },
......
...@@ -27,11 +27,15 @@ static const struct sof_dev_desc bxt_desc = { ...@@ -27,11 +27,15 @@ static const struct sof_dev_desc bxt_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &apl_chip_info, .chip_info = &apl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/apl",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-apl.ri", .default_fw_filename = "sof-apl.ri",
.nocodec_tplg_filename = "sof-apl-nocodec.tplg", .nocodec_tplg_filename = "sof-apl-nocodec.tplg",
...@@ -46,11 +50,15 @@ static const struct sof_dev_desc glk_desc = { ...@@ -46,11 +50,15 @@ static const struct sof_dev_desc glk_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &apl_chip_info, .chip_info = &apl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/glk",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-glk.ri", .default_fw_filename = "sof-glk.ri",
.nocodec_tplg_filename = "sof-glk-nocodec.tplg", .nocodec_tplg_filename = "sof-glk-nocodec.tplg",
......
...@@ -28,11 +28,15 @@ static const struct sof_dev_desc cnl_desc = { ...@@ -28,11 +28,15 @@ static const struct sof_dev_desc cnl_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &cnl_chip_info, .chip_info = &cnl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/cnl",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-cnl.ri", .default_fw_filename = "sof-cnl.ri",
.nocodec_tplg_filename = "sof-cnl-nocodec.tplg", .nocodec_tplg_filename = "sof-cnl-nocodec.tplg",
...@@ -48,11 +52,15 @@ static const struct sof_dev_desc cfl_desc = { ...@@ -48,11 +52,15 @@ static const struct sof_dev_desc cfl_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &cnl_chip_info, .chip_info = &cnl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/cnl",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-cfl.ri", .default_fw_filename = "sof-cfl.ri",
.nocodec_tplg_filename = "sof-cnl-nocodec.tplg", .nocodec_tplg_filename = "sof-cnl-nocodec.tplg",
...@@ -68,11 +76,15 @@ static const struct sof_dev_desc cml_desc = { ...@@ -68,11 +76,15 @@ static const struct sof_dev_desc cml_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &cnl_chip_info, .chip_info = &cnl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/cnl",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-cml.ri", .default_fw_filename = "sof-cml.ri",
.nocodec_tplg_filename = "sof-cnl-nocodec.tplg", .nocodec_tplg_filename = "sof-cnl-nocodec.tplg",
......
...@@ -28,11 +28,15 @@ static const struct sof_dev_desc icl_desc = { ...@@ -28,11 +28,15 @@ static const struct sof_dev_desc icl_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &icl_chip_info, .chip_info = &icl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/icl",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-icl.ri", .default_fw_filename = "sof-icl.ri",
.nocodec_tplg_filename = "sof-icl-nocodec.tplg", .nocodec_tplg_filename = "sof-icl-nocodec.tplg",
...@@ -47,11 +51,15 @@ static const struct sof_dev_desc jsl_desc = { ...@@ -47,11 +51,15 @@ static const struct sof_dev_desc jsl_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &jsl_chip_info, .chip_info = &jsl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/jsl",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-jsl.ri", .default_fw_filename = "sof-jsl.ri",
.nocodec_tplg_filename = "sof-jsl-nocodec.tplg", .nocodec_tplg_filename = "sof-jsl-nocodec.tplg",
......
...@@ -28,11 +28,15 @@ static const struct sof_dev_desc tgl_desc = { ...@@ -28,11 +28,15 @@ static const struct sof_dev_desc tgl_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &tgl_chip_info, .chip_info = &tgl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/tgl",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-tgl.ri", .default_fw_filename = "sof-tgl.ri",
.nocodec_tplg_filename = "sof-tgl-nocodec.tplg", .nocodec_tplg_filename = "sof-tgl-nocodec.tplg",
...@@ -48,11 +52,15 @@ static const struct sof_dev_desc tglh_desc = { ...@@ -48,11 +52,15 @@ static const struct sof_dev_desc tglh_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &tglh_chip_info, .chip_info = &tglh_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/tgl-h",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-tgl-h.ri", .default_fw_filename = "sof-tgl-h.ri",
.nocodec_tplg_filename = "sof-tgl-nocodec.tplg", .nocodec_tplg_filename = "sof-tgl-nocodec.tplg",
...@@ -67,11 +75,15 @@ static const struct sof_dev_desc ehl_desc = { ...@@ -67,11 +75,15 @@ static const struct sof_dev_desc ehl_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &ehl_chip_info, .chip_info = &ehl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/ehl",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-ehl.ri", .default_fw_filename = "sof-ehl.ri",
.nocodec_tplg_filename = "sof-ehl-nocodec.tplg", .nocodec_tplg_filename = "sof-ehl-nocodec.tplg",
...@@ -87,11 +99,15 @@ static const struct sof_dev_desc adls_desc = { ...@@ -87,11 +99,15 @@ static const struct sof_dev_desc adls_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &adls_chip_info, .chip_info = &adls_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/adl-s",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-adl-s.ri", .default_fw_filename = "sof-adl-s.ri",
.nocodec_tplg_filename = "sof-adl-nocodec.tplg", .nocodec_tplg_filename = "sof-adl-nocodec.tplg",
...@@ -107,11 +123,15 @@ static const struct sof_dev_desc adl_desc = { ...@@ -107,11 +123,15 @@ static const struct sof_dev_desc adl_desc = {
.resindex_imr_base = -1, .resindex_imr_base = -1,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &tgl_chip_info, .chip_info = &tgl_chip_info,
.ipc_supported_mask = BIT(SOF_IPC) | BIT(SOF_INTEL_IPC4),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
[SOF_INTEL_IPC4] = "intel/avs/adl",
}, },
.default_tplg_path = { .default_tplg_path = {
[SOF_IPC] = "intel/sof-tplg", [SOF_IPC] = "intel/sof-tplg",
[SOF_INTEL_IPC4] = "intel/avs-tplg",
}, },
.default_fw_filename = "sof-adl.ri", .default_fw_filename = "sof-adl.ri",
.nocodec_tplg_filename = "sof-adl-nocodec.tplg", .nocodec_tplg_filename = "sof-adl-nocodec.tplg",
......
...@@ -219,6 +219,8 @@ static const struct sof_dev_desc tng_desc = { ...@@ -219,6 +219,8 @@ static const struct sof_dev_desc tng_desc = {
.resindex_imr_base = 0, .resindex_imr_base = 0,
.irqindex_host_ipc = -1, .irqindex_host_ipc = -1,
.chip_info = &tng_chip_info, .chip_info = &tng_chip_info,
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "intel/sof", [SOF_IPC] = "intel/sof",
}, },
......
...@@ -440,6 +440,8 @@ static const struct snd_sof_dsp_ops sof_mt8195_ops = { ...@@ -440,6 +440,8 @@ static const struct snd_sof_dsp_ops sof_mt8195_ops = {
}; };
static const struct sof_dev_desc sof_of_mt8195_desc = { static const struct sof_dev_desc sof_of_mt8195_desc = {
.ipc_supported_mask = BIT(SOF_IPC),
.ipc_default = SOF_IPC,
.default_fw_path = { .default_fw_path = {
[SOF_IPC] = "mediatek/sof", [SOF_IPC] = "mediatek/sof",
}, },
......
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