Commit 0d624275 authored by Vaibhav Bedia's avatar Vaibhav Bedia Committed by Mark Brown

ASoC: Davinci: McASP: Flush the FIFO before enabling

FIFO should be flushed before it is enabled for the first time.
This fixes the I/O errors reported by the ASoC core on a fresh boot
Signed-off-by: default avatarVaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: default avatarHebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 0865a75d
...@@ -380,14 +380,20 @@ static void mcasp_start_tx(struct davinci_audio_dev *dev) ...@@ -380,14 +380,20 @@ static void mcasp_start_tx(struct davinci_audio_dev *dev)
static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream) static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
{ {
if (stream == SNDRV_PCM_STREAM_PLAYBACK) { if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (dev->txnumevt) /* enable FIFO */ if (dev->txnumevt) { /* enable FIFO */
mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
FIFO_ENABLE);
mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
FIFO_ENABLE); FIFO_ENABLE);
}
mcasp_start_tx(dev); mcasp_start_tx(dev);
} else { } else {
if (dev->rxnumevt) /* enable FIFO */ if (dev->rxnumevt) { /* enable FIFO */
mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
FIFO_ENABLE);
mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
FIFO_ENABLE); FIFO_ENABLE);
}
mcasp_start_rx(dev); mcasp_start_rx(dev);
} }
} }
......
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