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Commit 0dc48495 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'renesas-dt-for-v3.20' of... 

Merge tag 'renesas-dt-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Renesas ARM Based SoC DT Updates for v3.20" from Simon Horman:

* Use clock-indices instead of deprecated renesas,clock-indices
* Prepare for r8a73a4 multiplatform support
* Increase clock coverage for r8a779[014]
* Correct r8a7779 clock usage
* Correct LAN9220 VDDVARIO voltage on ape6evm
* Correct QSPI SPI-Flash mode of lager and koelsch
* Correct flash partition label and size on koelsch
* Correct mask for GIC PPI interrupts on r8a779[14]
* Correct BSC bus range on ape6evm-reference

* tag 'renesas-dt-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (30 commits)
  ARM: shmobile: r8a7791: add MLB+ clock
  ARM: shmobile: r8a7790: add MLB+ clock
  ARM: shmobile: ape6evm: Fix LAN9220 VDDVARIO voltage
  ARM: shmobile: r8a73a4: Add r8a73a4-ape6evm.dtb to ARCH_SHMOBILE_MULTI
  ARM: shmobile: ape6evm: Add keypad to the device tree
  ARM: shmobile: ape6evm: Add LEDs to the device tree
  ARM: shmobile: ape6evm: synchronize dts with reference platform
  ARM: shmobile: ape6evm: fix compatible string for Ethernet controller
  ARM: shmobile: r8a7794: Add MMCIF clock to device tree
  ARM: shmobile: r8a7794: Add SDHI clocks to device tree
  ARM: shmobile: r8a7794: Add I2C clocks to device tree
  ARM: shmobile: r8a7779: Add TWD device to DTS
  ARM: shmobile: r8a7779: Use MSTP for SCIF clocks
  ARM: shmobile: r8a7779: Use R8A7779_CLK_P as SCIF parent clock
  ARM: shmobile: r8a7794: Add QSPI clock to device tree
  ARM: shmobile: lager: Fix QSPI mode of SPI-Flash into mode3
  ARM: shmobile: r8a7794: Add SYS-DMAC clocks to device tree
  ARM: shmobile: r8a7791: Add IPMMU-SGX clock to device tree
  ARM: shmobile: koelsch: Fix QSPI mode of SPI-Flash into mode3
  ARM: shmobile: r8a7794: Add USBDMAC[01] clocks to device tree
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 318a68f2 7408d306
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Showing with 333 additions and 81 deletions
arch/arm/boot/dts/Makefile
View file @ 0dc48495
......@@ -416,6 +416,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
sh73a0-kzm9g-reference.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
......
arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
View file @ 0dc48495
......@@ -67,7 +67,7 @@ lbsc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
ranges = <0 0 0 0x20000000>;
};
};
......
arch/arm/boot/dts/r8a73a4-ape6evm.dts
View file @ 0dc48495
......@@ -10,14 +10,20 @@
/dts-v1/;
#include "r8a73a4.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "APE6EVM";
compatible = "renesas,ape6evm", "renesas,r8a73a4";
aliases {
serial0 = &scifa0;
};
chosen {
bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
stdout-path = &scifa0;
};
memory@40000000 {
......@@ -30,7 +36,35 @@ memory@200000000 {
reg = <2 0x00000000 0 0x40000000>;
};
ape6evm_fixed_3v3: fixedregulator@0 {
vcc_mmc0: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "MMC0 Vcc";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
vcc_sdhi0: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
/* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */
ape6evm_fixed_1v8: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ape6evm_fixed_3v3: regulator@3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
......@@ -39,11 +73,13 @@ ape6evm_fixed_3v3: fixedregulator@0 {
};
lbsc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x20000000>;
ethernet@8000000 {
compatible = "smsc,lan9118", "smsc,lan9115";
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x08000000 0x1000>;
interrupt-parent = <&irqc1>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
......@@ -52,7 +88,75 @@ ethernet@8000000 {
smsc,irq-active-high;
smsc,irq-push-pull;
vdd33a-supply = <&ape6evm_fixed_3v3>;
vddvario-supply = <&ape6evm_fixed_3v3>;
vddvario-supply = <&ape6evm_fixed_1v8>;
};
};
leds {
compatible = "gpio-leds";
led1 {
gpios = <&pfc 28 GPIO_ACTIVE_LOW>;
label = "GNSS_EN";
};
led2 {
gpios = <&pfc 126 GPIO_ACTIVE_LOW>;
label = "NFC_NRST";
};
led3 {
gpios = <&pfc 132 GPIO_ACTIVE_LOW>;
label = "GNSS_NRST";
};
led4 {
gpios = <&pfc 232 GPIO_ACTIVE_LOW>;
label = "BT_WAKEUP";
};
led5 {
gpios = <&pfc 250 GPIO_ACTIVE_LOW>;
label = "STROBE";
};
led6 {
gpios = <&pfc 288 GPIO_ACTIVE_LOW>;
label = "BBRESETOUT";
};
};
keyboard {
compatible = "gpio-keys";
zero-key {
gpios = <&pfc 324 GPIO_ACTIVE_LOW>;
linux,code = <KEY_0>;
label = "S16";
};
menu-key {
gpios = <&pfc 325 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
label = "S17";
};
home-key {
gpios = <&pfc 326 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
label = "S18";
};
back-key {
gpios = <&pfc 327 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
label = "S19";
};
volup-key {
gpios = <&pfc 328 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
label = "S20";
};
voldown-key {
gpios = <&pfc 329 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
label = "S21";
};
};
};
......@@ -79,3 +183,64 @@ &cpu0 {
>;
voltage-tolerance = <1>; /* 1% */
};
&cmt1 {
status = "okay";
};
&pfc {
scifa0_pins: serial0 {
renesas,groups = "scifa0_data";
renesas,function = "scifa0";
};
mmc0_pins: mmc {
renesas,groups = "mmc0_data8", "mmc0_ctrl";
renesas,function = "mmc0";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
renesas,function = "sdhi0";
};
sdhi1_pins: sd1 {
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1";
};
};
&mmcif0 {
vmmc-supply = <&vcc_mmc0>;
bus-width = <8>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
status = "okay";
};
&scifa0 {
pinctrl-0 = <&scifa0_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
vmmc-supply = <&vcc_sdhi0>;
bus-width = <4>;
toshiba,mmc-wrprotect-disable;
pinctrl-names = "default";
pinctrl-0 = <&sdhi0_pins>;
status = "okay";
};
&sdhi1 {
vmmc-supply = <&ape6evm_fixed_3v3>;
bus-width = <4>;
broken-cd;
toshiba,mmc-wrprotect-disable;
pinctrl-names = "default";
pinctrl-0 = <&sdhi1_pins>;
status = "okay";
};
arch/arm/boot/dts/r8a7740.dtsi
View file @ 0dc48495
......@@ -453,7 +453,7 @@ subck_clks: subck_clks@e6150080 {
reg = <0xe6150080 4>;
clocks = <&sub_clk>, <&sub_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
>;
clock-output-names =
......@@ -468,7 +468,7 @@ mstp1_clks: mstp1_clks@e6150134 {
<&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
<&cpg_clocks R8A7740_CLK_B>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
R8A7740_CLK_LCDC0
......@@ -489,7 +489,7 @@ mstp2_clks: mstp2_clks@e6150138 {
<&sub_clk>, <&sub_clk>, <&sub_clk>,
<&sub_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
R8A7740_CLK_SCIFA7
R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
......@@ -518,7 +518,7 @@ mstp3_clks: mstp3_clks@e615013c {
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
......@@ -535,7 +535,7 @@ mstp4_clks: mstp4_clks@e6150140 {
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7740_CLK_USBH R8A7740_CLK_SDHI2
R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
>;
......
arch/arm/boot/dts/r8a7779.dtsi
View file @ 0dc48495
......@@ -12,6 +12,7 @@
/include/ "skeleton.dtsi"
#include <dt-bindings/clock/r8a7779-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
......@@ -62,6 +63,14 @@ gic: interrupt-controller@f0001000 {
<0xf0000100 0x100>;
};
timer@f0000600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf0000600 0x20>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg_clocks R8A7779_CLK_ZS>;
};
gpio0: gpio@ffc40000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
reg = <0xffc40000 0x2c>;
......@@ -200,7 +209,7 @@ scif0: serial@ffe40000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe40000 0x100>;
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
clock-names = "sci_ick";
status = "disabled";
};
......@@ -209,7 +218,7 @@ scif1: serial@ffe41000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe41000 0x100>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
clock-names = "sci_ick";
status = "disabled";
};
......@@ -218,7 +227,7 @@ scif2: serial@ffe42000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe42000 0x100>;
interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
clock-names = "sci_ick";
status = "disabled";
};
......@@ -227,7 +236,7 @@ scif3: serial@ffe43000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe43000 0x100>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
clock-names = "sci_ick";
status = "disabled";
};
......@@ -236,7 +245,7 @@ scif4: serial@ffe44000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe44000 0x100>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
clock-names = "sci_ick";
status = "disabled";
};
......@@ -245,7 +254,7 @@ scif5: serial@ffe45000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe45000 0x100>;
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
clock-names = "sci_ick";
status = "disabled";
};
......@@ -464,18 +473,18 @@ mstp0_clks: clocks@ffc80030 {
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_S>,
<&cpg_clocks R8A7779_CLK_S>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_S1>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_P>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7779_CLK_HSPI R8A7779_CLK_TMU2
R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
......@@ -506,7 +515,7 @@ mstp1_clks: clocks@ffc80034 {
<&cpg_clocks R8A7779_CLK_P>,
<&cpg_clocks R8A7779_CLK_S>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7779_CLK_USB01 R8A7779_CLK_USB2
R8A7779_CLK_DU R8A7779_CLK_VIN2
R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
......@@ -527,7 +536,7 @@ mstp3_clks: clocks@ffc8003c {
clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
<&s4_clk>, <&s4_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
......
arch/arm/boot/dts/r8a7790-lager.dts
View file @ 0dc48495
......@@ -397,6 +397,8 @@ flash: flash@0 {
spi-max-frequency = <30000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-cpha;
spi-cpol;
m25p,fast-read;
partition@0 {
......
arch/arm/boot/dts/r8a7790.dtsi
View file @ 0dc48495
......@@ -1054,7 +1054,7 @@ mstp0_clks: mstp0_clks@e6150130 {
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
clocks = <&mp_clk>;
#clock-cells = <1>;
renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
clock-indices = <R8A7790_CLK_MSIOF0>;
clock-output-names = "msiof0";
};
mstp1_clks: mstp1_clks@e6150134 {
......@@ -1065,7 +1065,7 @@ mstp1_clks: mstp1_clks@e6150134 {
<&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
......@@ -1087,7 +1087,7 @@ mstp2_clks: mstp2_clks@e6150138 {
<&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
<&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
......@@ -1106,7 +1106,7 @@ mstp3_clks: mstp3_clks@e615013c {
<&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
<&hp_clk>, <&hp_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
......@@ -1123,8 +1123,10 @@ mstp5_clks: mstp5_clks@e6150144 {
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
#clock-cells = <1>;
renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
clock-indices = <
R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
R8A7790_CLK_THERMAL R8A7790_CLK_PWM
>;
clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
};
mstp7_clks: mstp7_clks@e615014c {
......@@ -1134,7 +1136,7 @@ mstp7_clks: mstp7_clks@e615014c {
<&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
<&zx_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
......@@ -1147,16 +1149,17 @@ R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
mstp8_clks: mstp8_clks@e6150990 {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
<&zs_clk>, <&zs_clk>;
clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
<&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
R8A7790_CLK_SATA0
clock-indices = <
R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
>;
clock-output-names =
"vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
"mlb", "vin3", "vin2", "vin1", "vin0", "ether",
"sata1", "sata0";
};
mstp9_clks: mstp9_clks@e6150994 {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
......@@ -1166,7 +1169,7 @@ mstp9_clks: mstp9_clks@e6150994 {
<&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
......
arch/arm/boot/dts/r8a7791-koelsch.dts
View file @ 0dc48495
......@@ -444,6 +444,8 @@ flash: flash@0 {
spi-max-frequency = <30000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-cpha;
spi-cpol;
m25p,fast-read;
partition@0 {
......@@ -452,13 +454,13 @@ partition@0 {
read-only;
};
partition@80000 {
label = "bootenv";
reg = <0x00080000 0x00080000>;
label = "user";
reg = <0x00080000 0x00580000>;
read-only;
};
partition@100000 {
label = "data";
reg = <0x00100000 0x03f00000>;
partition@600000 {
label = "flash";
reg = <0x00600000 0x03a00000>;
};
};
};
......
arch/arm/boot/dts/r8a7791.dtsi
View file @ 0dc48495
......@@ -78,7 +78,7 @@ gic: interrupt-controller@f1001000 {
<0 0xf1002000 0 0x1000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
gpio0: gpio@e6050000 {
......@@ -186,10 +186,10 @@ thermal@e61f0000 {
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
cmt0: timer@ffca0000 {
......@@ -1062,7 +1062,7 @@ mstp0_clks: mstp0_clks@e6150130 {
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
clocks = <&mp_clk>;
#clock-cells = <1>;
renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
clock-indices = <R8A7791_CLK_MSIOF0>;
clock-output-names = "msiof0";
};
mstp1_clks: mstp1_clks@e6150134 {
......@@ -1073,7 +1073,7 @@ mstp1_clks: mstp1_clks@e6150134 {
<&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
<&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
......@@ -1093,7 +1093,7 @@ mstp2_clks: mstp2_clks@e6150138 {
<&mp_clk>, <&mp_clk>, <&mp_clk>,
<&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
......@@ -1111,7 +1111,7 @@ mstp3_clks: mstp3_clks@e615013c {
<&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
<&hp_clk>, <&hp_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
......@@ -1127,8 +1127,10 @@ mstp5_clks: mstp5_clks@e6150144 {
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
#clock-cells = <1>;
renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
clock-indices = <
R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
R8A7791_CLK_THERMAL R8A7791_CLK_PWM
>;
clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
};
mstp7_clks: mstp7_clks@e615014c {
......@@ -1138,7 +1140,7 @@ mstp7_clks: mstp7_clks@e615014c {
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
<&zx_clk>, <&zx_clk>, <&zx_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
......@@ -1152,15 +1154,17 @@ R8A7791_CLK_LVDS0
mstp8_clks: mstp8_clks@e6150990 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
<&zs_clk>;
clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
<&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
>;
clock-output-names =
"vin2", "vin1", "vin0", "ether", "sata1", "sata0";
"ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
"sata1", "sata0";
};
mstp9_clks: mstp9_clks@e6150994 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
......@@ -1171,7 +1175,7 @@ mstp9_clks: mstp9_clks@e6150994 {
<&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
<&hp_clk>, <&hp_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
......@@ -1221,7 +1225,7 @@ mstp11_clks: mstp11_clks@e615099c {
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
>;
clock-output-names = "scifa3", "scifa4", "scifa5";
......
arch/arm/boot/dts/r8a7794.dtsi
View file @ 0dc48495
......@@ -47,7 +47,7 @@ gic: interrupt-controller@f1001000 {
<0 0xf1002000 0 0x1000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
cmt0: timer@ffca0000 {
......@@ -84,10 +84,10 @@ cmt1: timer@e6130000 {
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
irqc0: interrupt-controller@e61c0000 {
......@@ -293,6 +293,28 @@ cpg_clocks: cpg_clocks@e6150000 {
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z";
};
/* Variable factor clocks */
sd1_clk: sd2_clk@e6150078 {
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150078 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sd1";
};
sd2_clk: sd3_clk@e615007c {
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe615007c 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "sd2";
};
mmc0_clk: mmc0_clk@e6150240 {
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
reg = <0 0xe6150240 0 4>;
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-output-names = "mmc0";
};
/* Fixed factor clocks */
pll1_div2_clk: pll1_div2_clk {
......@@ -455,7 +477,7 @@ mstp0_clks: mstp0_clks@e6150130 {
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
clocks = <&mp_clk>;
#clock-cells = <1>;
renesas,clock-indices = <R8A7794_CLK_MSIOF0>;
clock-indices = <R8A7794_CLK_MSIOF0>;
clock-output-names = "msiof0";
};
mstp1_clks: mstp1_clks@e6150134 {
......@@ -465,7 +487,7 @@ mstp1_clks: mstp1_clks@e6150134 {
<&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
<&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
......@@ -479,41 +501,51 @@ mstp2_clks: mstp2_clks@e6150138 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
<&mp_clk>, <&mp_clk>, <&mp_clk>;
<&mp_clk>, <&mp_clk>, <&mp_clk>,
<&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
>;
clock-output-names =
"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
"scifb1", "msiof1", "scifb2";
"scifb1", "msiof1", "scifb2",
"sys-dmac1", "sys-dmac0";
};
mstp3_clks: mstp3_clks@e615013c {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
clocks = <&rclk_clk>;
clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
<&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7794_CLK_CMT1
clock-indices = <
R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
>;
clock-output-names =
"cmt1";
"sdhi2", "sdhi1", "sdhi0",
"mmcif0", "cmt1", "usbdmac0", "usbdmac1";
};
mstp7_clks: mstp7_clks@e615014c {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
clocks = <&mp_clk>, <&mp_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
R8A7794_CLK_SCIF0
>;
clock-output-names =
"ehci", "hsusb",
"hscif2", "scif5", "scif4", "hscif1", "hscif0",
"scif3", "scif2", "scif1", "scif0";
};
......@@ -522,18 +554,32 @@ mstp8_clks: mstp8_clks@e6150990 {
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
>;
clock-output-names =
"vin1", "vin0", "ether";
};
mstp9_clks: mstp9_clks@e6150994 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1
R8A7794_CLK_I2C0
>;
clock-output-names =
"qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
};
mstp11_clks: mstp11_clks@e615099c {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
clock-indices = <
R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
>;
clock-output-names = "scifa3", "scifa4", "scifa5";
......
include/dt-bindings/clock/r8a7790-clock.h
View file @ 0dc48495
......@@ -97,6 +97,7 @@
#define R8A7790_CLK_LVDS0 26
/* MSTP8 */
#define R8A7790_CLK_MLB 2
#define R8A7790_CLK_VIN3 8
#define R8A7790_CLK_VIN2 9
#define R8A7790_CLK_VIN1 10
......
include/dt-bindings/clock/r8a7791-clock.h
View file @ 0dc48495
......@@ -91,6 +91,8 @@
#define R8A7791_CLK_LVDS0 26
/* MSTP8 */
#define R8A7791_CLK_IPMMU_SGX 0
#define R8A7791_CLK_MLB 2
#define R8A7791_CLK_VIN2 9
#define R8A7791_CLK_VIN1 10
#define R8A7791_CLK_VIN0 11
......
include/dt-bindings/clock/r8a7794-clock.h
View file @ 0dc48495
......@@ -48,15 +48,25 @@
#define R8A7794_CLK_SCIFB1 7
#define R8A7794_CLK_MSIOF1 8
#define R8A7794_CLK_SCIFB2 16
#define R8A7794_CLK_SYS_DMAC1 18
#define R8A7794_CLK_SYS_DMAC0 19
/* MSTP3 */
#define R8A7794_CLK_SDHI2 11
#define R8A7794_CLK_SDHI1 12
#define R8A7794_CLK_SDHI0 14
#define R8A7794_CLK_MMCIF0 15
#define R8A7794_CLK_CMT1 29
#define R8A7794_CLK_USBDMAC0 30
#define R8A7794_CLK_USBDMAC1 31
/* MSTP5 */
#define R8A7794_CLK_THERMAL 22
#define R8A7794_CLK_PWM 23
/* MSTP7 */
#define R8A7794_CLK_EHCI 3
#define R8A7794_CLK_HSUSB 4
#define R8A7794_CLK_HSCIF2 13
#define R8A7794_CLK_SCIF5 14
#define R8A7794_CLK_SCIF4 15
......@@ -80,6 +90,13 @@
#define R8A7794_CLK_GPIO2 10
#define R8A7794_CLK_GPIO1 11
#define R8A7794_CLK_GPIO0 12
#define R8A7794_CLK_QSPI_MOD 17
#define R8A7794_CLK_I2C5 25
#define R8A7794_CLK_I2C4 27
#define R8A7794_CLK_I2C3 28
#define R8A7794_CLK_I2C2 29
#define R8A7794_CLK_I2C1 30
#define R8A7794_CLK_I2C0 31
/* MSTP11 */
#define R8A7794_CLK_SCIFA3 6
......
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